1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../hikey_def.h" 12 13 /* 14 * Generic platform constants 15 */ 16 17 /* Size of cacheable stacks */ 18 #define PLATFORM_STACK_SIZE 0x800 19 20 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 21 22 #define PLATFORM_CACHE_LINE_SIZE 64 23 #define PLATFORM_CLUSTER_COUNT 2 24 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 25 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 26 PLATFORM_CORE_COUNT_PER_CLUSTER) 27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 28 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 29 PLATFORM_CLUSTER_COUNT + 1) 30 31 #define PLAT_MAX_RET_STATE 1 32 #define PLAT_MAX_OFF_STATE 2 33 34 #define MAX_IO_DEVICES 3 35 #define MAX_IO_HANDLES 4 36 /* eMMC RPMB and eMMC User Data */ 37 #define MAX_IO_BLOCK_DEVICES 2 38 39 /* GIC related constants (no GICR in GIC-400) */ 40 #define PLAT_ARM_GICD_BASE 0xF6801000 41 #define PLAT_ARM_GICC_BASE 0xF6802000 42 #define PLAT_ARM_GICH_BASE 0xF6804000 43 #define PLAT_ARM_GICV_BASE 0xF6806000 44 45 46 /* 47 * Platform memory map related constants 48 */ 49 50 /* 51 * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). 52 */ 53 #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) 54 #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) 55 #define BL1_XG2RAM0_OFFSET 0x1000 56 57 /* 58 * BL1 specific defines. 59 * 60 * Both loader and BL1_RO region stay in SRAM since they are used to simulate 61 * ROM. 62 * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 63 * 64 * ++++++++++ 0xF980_0000 65 * + loader + 66 * ++++++++++ 0xF980_1000 67 * + BL1_RO + 68 * ++++++++++ 0xF981_0000 69 * + BL1_RW + 70 * ++++++++++ 0xF989_8000 71 */ 72 #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) 73 #define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) 74 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ 75 #define BL1_RW_SIZE (0x00088000) 76 #define BL1_RW_LIMIT (0xF9898000) 77 78 /* 79 * BL2 specific defines. 80 */ 81 #define BL2_BASE (BL1_RW_BASE + 0x8000) /* 0xf981_8000 */ 82 #define BL2_LIMIT (BL2_BASE + 0x40000) 83 84 /* 85 * SCP_BL2 specific defines. 86 * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer 87 * at 0x0100_0000. Then BL2 will parse the sections and loaded them into 88 * predefined separated buffers. 89 */ 90 #define SCP_BL2_BASE (DDR_BASE + 0x01000000) 91 #define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) 92 #define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) 93 94 /* 95 * BL31 specific defines. 96 */ 97 #define BL31_BASE BL2_LIMIT 98 #define BL31_LIMIT 0xF9898000 99 100 /* 101 * BL3-2 specific defines. 102 */ 103 104 /* 105 * The TSP currently executes from TZC secured area of DRAM or SRAM. 106 */ 107 #define BL32_SRAM_BASE BL31_LIMIT 108 #define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ 109 110 #define BL32_DRAM_BASE DDR_SEC_BASE 111 #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 112 113 #if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) 114 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 115 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 116 #define BL32_BASE BL32_DRAM_BASE 117 #define BL32_LIMIT BL32_DRAM_LIMIT 118 #elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) 119 #define TSP_SEC_MEM_BASE BL32_SRAM_BASE 120 #define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) 121 #define BL32_BASE BL32_SRAM_BASE 122 #define BL32_LIMIT BL32_SRAM_LIMIT 123 #else 124 #error "Currently unsupported HIKEY_TSP_LOCATION_ID value" 125 #endif 126 127 #define NS_BL1U_BASE (BL2_BASE) 128 #define NS_BL1U_SIZE (0x00010000) 129 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 130 131 /* 132 * Platform specific page table and MMU setup constants 133 */ 134 #define ADDR_SPACE_SIZE (1ull << 32) 135 136 #if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL32 137 #define MAX_XLAT_TABLES 3 138 #endif 139 140 #if IMAGE_BL31 141 #define MAX_XLAT_TABLES 4 142 #endif 143 144 #define MAX_MMAP_REGIONS 16 145 146 #define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) 147 148 /* 149 * Declarations and constants to access the mailboxes safely. Each mailbox is 150 * aligned on the biggest cache line size in the platform. This is known only 151 * to the platform as it might have a combination of integrated and external 152 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 153 * line at any cache level. They could belong to different cpus/clusters & 154 * get written while being protected by different locks causing corruption of 155 * a valid mailbox address. 156 */ 157 #define CACHE_WRITEBACK_SHIFT 6 158 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 159 160 #endif /* __PLATFORM_DEF_H__ */ 161