1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../hikey_def.h" 12 13 /* 14 * Platform binary types for linking 15 */ 16 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 17 #define PLATFORM_LINKER_ARCH aarch64 18 19 20 /* 21 * Generic platform constants 22 */ 23 24 /* Size of cacheable stacks */ 25 #define PLATFORM_STACK_SIZE 0x800 26 27 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 28 29 #define PLATFORM_CACHE_LINE_SIZE 64 30 #define PLATFORM_CLUSTER_COUNT 2 31 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 32 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 33 PLATFORM_CORE_COUNT_PER_CLUSTER) 34 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 35 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 36 PLATFORM_CLUSTER_COUNT + 1) 37 38 #define PLAT_MAX_RET_STATE 1 39 #define PLAT_MAX_OFF_STATE 2 40 41 #define MAX_IO_DEVICES 3 42 #define MAX_IO_HANDLES 4 43 /* eMMC RPMB and eMMC User Data */ 44 #define MAX_IO_BLOCK_DEVICES 2 45 46 /* GIC related constants (no GICR in GIC-400) */ 47 #define PLAT_ARM_GICD_BASE 0xF6801000 48 #define PLAT_ARM_GICC_BASE 0xF6802000 49 #define PLAT_ARM_GICH_BASE 0xF6804000 50 #define PLAT_ARM_GICV_BASE 0xF6806000 51 52 53 /* 54 * Platform memory map related constants 55 */ 56 57 /* 58 * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). 59 */ 60 #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) 61 #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) 62 #define BL1_XG2RAM0_OFFSET 0x1000 63 64 /* 65 * BL1 specific defines. 66 * 67 * Both loader and BL1_RO region stay in SRAM since they are used to simulate 68 * ROM. 69 * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 70 * 71 * ++++++++++ 0xF980_0000 72 * + loader + 73 * ++++++++++ 0xF980_1000 74 * + BL1_RO + 75 * ++++++++++ 0xF981_0000 76 * + BL1_RW + 77 * ++++++++++ 0xF989_8000 78 */ 79 #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) 80 #define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) 81 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ 82 #define BL1_RW_SIZE (0x00088000) 83 #define BL1_RW_LIMIT (0xF9898000) 84 85 /* 86 * BL2 specific defines. 87 */ 88 #define BL2_BASE (BL1_RW_BASE + 0x8000) /* 0xf981_8000 */ 89 #define BL2_LIMIT (BL2_BASE + 0x40000) 90 91 /* 92 * SCP_BL2 specific defines. 93 * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer 94 * at 0x0100_0000. Then BL2 will parse the sections and loaded them into 95 * predefined separated buffers. 96 */ 97 #define SCP_BL2_BASE (DDR_BASE + 0x01000000) 98 #define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) 99 #define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) 100 101 /* 102 * BL31 specific defines. 103 */ 104 #define BL31_BASE BL2_LIMIT 105 #define BL31_LIMIT 0xF9898000 106 107 #define NS_BL1U_BASE (BL2_BASE) 108 #define NS_BL1U_SIZE (0x00010000) 109 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 110 111 /* 112 * Platform specific page table and MMU setup constants 113 */ 114 #define ADDR_SPACE_SIZE (1ull << 32) 115 116 #if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 117 #define MAX_XLAT_TABLES 3 118 #endif 119 120 #define MAX_MMAP_REGIONS 16 121 122 #define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000) 123 124 /* 125 * Declarations and constants to access the mailboxes safely. Each mailbox is 126 * aligned on the biggest cache line size in the platform. This is known only 127 * to the platform as it might have a combination of integrated and external 128 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 129 * line at any cache level. They could belong to different cpus/clusters & 130 * get written while being protected by different locks causing corruption of 131 * a valid mailbox address. 132 */ 133 #define CACHE_WRITEBACK_SHIFT 6 134 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 135 136 #endif /* __PLATFORM_DEF_H__ */ 137