1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <hikey_def.h> 13 #include <hikey_layout.h> /* BL memory region sizes, etc */ 14 #include <tbbr_img_def.h> 15 #include <utils_def.h> 16 17 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 18 #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 19 20 /* 21 * Generic platform constants 22 */ 23 24 /* Size of cacheable stacks */ 25 #define PLATFORM_STACK_SIZE 0x1000 26 27 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 28 29 #define PLATFORM_CACHE_LINE_SIZE 64 30 #define PLATFORM_CLUSTER_COUNT 2 31 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 32 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 33 PLATFORM_CORE_COUNT_PER_CLUSTER) 34 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) 35 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 36 PLATFORM_CLUSTER_COUNT + 1) 37 38 #define PLAT_MAX_RET_STATE U(1) 39 #define PLAT_MAX_OFF_STATE U(2) 40 41 #define MAX_IO_DEVICES 3 42 #define MAX_IO_HANDLES 4 43 /* eMMC RPMB and eMMC User Data */ 44 #define MAX_IO_BLOCK_DEVICES 2 45 46 /* GIC related constants (no GICR in GIC-400) */ 47 #define PLAT_ARM_GICD_BASE 0xF6801000 48 #define PLAT_ARM_GICC_BASE 0xF6802000 49 #define PLAT_ARM_GICH_BASE 0xF6804000 50 #define PLAT_ARM_GICV_BASE 0xF6806000 51 52 /* 53 * Platform specific page table and MMU setup constants 54 */ 55 #define ADDR_SPACE_SIZE (1ULL << 32) 56 57 #if defined(IMAGE_BL1) || defined(IMAGE_BL32) 58 #define MAX_XLAT_TABLES 3 59 #endif 60 61 #ifdef IMAGE_BL31 62 #define MAX_XLAT_TABLES 4 63 #endif 64 65 #ifdef IMAGE_BL2 66 #define MAX_XLAT_TABLES 4 67 #endif 68 69 #define MAX_MMAP_REGIONS 16 70 71 /* 72 * Declarations and constants to access the mailboxes safely. Each mailbox is 73 * aligned on the biggest cache line size in the platform. This is known only 74 * to the platform as it might have a combination of integrated and external 75 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 76 * line at any cache level. They could belong to different cpus/clusters & 77 * get written while being protected by different locks causing corruption of 78 * a valid mailbox address. 79 */ 80 #define CACHE_WRITEBACK_SHIFT 6 81 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 82 83 #endif /* PLATFORM_DEF_H */ 84