108b167e9SHaojian Zhuang /* 2103c213cSHaojian Zhuang * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 308b167e9SHaojian Zhuang * 408b167e9SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 508b167e9SHaojian Zhuang */ 608b167e9SHaojian Zhuang 708b167e9SHaojian Zhuang #ifndef __PLATFORM_DEF_H__ 808b167e9SHaojian Zhuang #define __PLATFORM_DEF_H__ 908b167e9SHaojian Zhuang 1008b167e9SHaojian Zhuang #include <arch.h> 114368ae07SMichael Brandl #include <common_def.h> 124368ae07SMichael Brandl #include <hikey_def.h> 134368ae07SMichael Brandl #include <hikey_layout.h> /* BL memory region sizes, etc */ 144368ae07SMichael Brandl #include <tbbr_img_def.h> 1508b167e9SHaojian Zhuang 162de0c5ccSVictor Chong /* Special value used to verify platform parameters from BL2 to BL3-1 */ 172de0c5ccSVictor Chong #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 182de0c5ccSVictor Chong 1908b167e9SHaojian Zhuang /* 2008b167e9SHaojian Zhuang * Generic platform constants 2108b167e9SHaojian Zhuang */ 2208b167e9SHaojian Zhuang 2308b167e9SHaojian Zhuang /* Size of cacheable stacks */ 24*e59a3bffSTeddy Reed #define PLATFORM_STACK_SIZE 0x1000 2508b167e9SHaojian Zhuang 2608b167e9SHaojian Zhuang #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 2708b167e9SHaojian Zhuang 2808b167e9SHaojian Zhuang #define PLATFORM_CACHE_LINE_SIZE 64 2908b167e9SHaojian Zhuang #define PLATFORM_CLUSTER_COUNT 2 3008b167e9SHaojian Zhuang #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 3108b167e9SHaojian Zhuang #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 3208b167e9SHaojian Zhuang PLATFORM_CORE_COUNT_PER_CLUSTER) 334368ae07SMichael Brandl #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) 3408b167e9SHaojian Zhuang #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 3508b167e9SHaojian Zhuang PLATFORM_CLUSTER_COUNT + 1) 3608b167e9SHaojian Zhuang 3708b167e9SHaojian Zhuang #define PLAT_MAX_RET_STATE 1 3808b167e9SHaojian Zhuang #define PLAT_MAX_OFF_STATE 2 3908b167e9SHaojian Zhuang 4008b167e9SHaojian Zhuang #define MAX_IO_DEVICES 3 4108b167e9SHaojian Zhuang #define MAX_IO_HANDLES 4 4208b167e9SHaojian Zhuang /* eMMC RPMB and eMMC User Data */ 4308b167e9SHaojian Zhuang #define MAX_IO_BLOCK_DEVICES 2 4408b167e9SHaojian Zhuang 4508b167e9SHaojian Zhuang /* GIC related constants (no GICR in GIC-400) */ 4608b167e9SHaojian Zhuang #define PLAT_ARM_GICD_BASE 0xF6801000 4708b167e9SHaojian Zhuang #define PLAT_ARM_GICC_BASE 0xF6802000 4808b167e9SHaojian Zhuang #define PLAT_ARM_GICH_BASE 0xF6804000 4908b167e9SHaojian Zhuang #define PLAT_ARM_GICV_BASE 0xF6806000 5008b167e9SHaojian Zhuang 5108b167e9SHaojian Zhuang /* 5208b167e9SHaojian Zhuang * Platform specific page table and MMU setup constants 5308b167e9SHaojian Zhuang */ 545724481fSDavid Cunado #define ADDR_SPACE_SIZE (1ULL << 32) 5508b167e9SHaojian Zhuang 56e8a87acdSRoberto Vargas #if defined(IMAGE_BL1) || defined(IMAGE_BL32) 5708b167e9SHaojian Zhuang #define MAX_XLAT_TABLES 3 5808b167e9SHaojian Zhuang #endif 5908b167e9SHaojian Zhuang 60e8a87acdSRoberto Vargas #ifdef IMAGE_BL31 613b6e88a2SVictor Chong #define MAX_XLAT_TABLES 4 623b6e88a2SVictor Chong #endif 633b6e88a2SVictor Chong 64e8a87acdSRoberto Vargas #ifdef IMAGE_BL2 65b16bb16eSVictor Chong #define MAX_XLAT_TABLES 4 66b16bb16eSVictor Chong #endif 67b16bb16eSVictor Chong 6808b167e9SHaojian Zhuang #define MAX_MMAP_REGIONS 16 6908b167e9SHaojian Zhuang 7008b167e9SHaojian Zhuang /* 7108b167e9SHaojian Zhuang * Declarations and constants to access the mailboxes safely. Each mailbox is 7208b167e9SHaojian Zhuang * aligned on the biggest cache line size in the platform. This is known only 7308b167e9SHaojian Zhuang * to the platform as it might have a combination of integrated and external 7408b167e9SHaojian Zhuang * caches. Such alignment ensures that two maiboxes do not sit on the same cache 7508b167e9SHaojian Zhuang * line at any cache level. They could belong to different cpus/clusters & 7608b167e9SHaojian Zhuang * get written while being protected by different locks causing corruption of 7708b167e9SHaojian Zhuang * a valid mailbox address. 7808b167e9SHaojian Zhuang */ 7908b167e9SHaojian Zhuang #define CACHE_WRITEBACK_SHIFT 6 8008b167e9SHaojian Zhuang #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 8108b167e9SHaojian Zhuang 8208b167e9SHaojian Zhuang #endif /* __PLATFORM_DEF_H__ */ 83