108b167e9SHaojian Zhuang/* 208b167e9SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 308b167e9SHaojian Zhuang * 408b167e9SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 508b167e9SHaojian Zhuang */ 608b167e9SHaojian Zhuang 7*c3cf06f1SAntonio Nino Diaz#ifndef PLAT_MACROS_S 8*c3cf06f1SAntonio Nino Diaz#define PLAT_MACROS_S 908b167e9SHaojian Zhuang 1008b167e9SHaojian Zhuang#include <cci.h> 11c3b5800bSAntonio Nino Diaz#include <gicv2.h> 1208b167e9SHaojian Zhuang#include <hi6220.h> 1308b167e9SHaojian Zhuang#include <platform_def.h> 1408b167e9SHaojian Zhuang 1508b167e9SHaojian Zhuang.section .rodata.gic_reg_name, "aS" 1608b167e9SHaojian Zhuanggicc_regs: 1708b167e9SHaojian Zhuang .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 1808b167e9SHaojian Zhuanggicd_pend_reg: 1900a64624SHaojian Zhuang .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 2008b167e9SHaojian Zhuangnewline: 2108b167e9SHaojian Zhuang .asciz "\n" 2208b167e9SHaojian Zhuangspacer: 2308b167e9SHaojian Zhuang .asciz ":\t\t0x" 2408b167e9SHaojian Zhuang 2508b167e9SHaojian Zhuang.section .rodata.cci_reg_name, "aS" 2608b167e9SHaojian Zhuangcci_iface_regs: 2708b167e9SHaojian Zhuang .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 2808b167e9SHaojian Zhuang 2908b167e9SHaojian Zhuang/* --------------------------------------------- 3008b167e9SHaojian Zhuang * The below macro prints out relevant GIC 3108b167e9SHaojian Zhuang * registers whenever an unhandled exception is 3208b167e9SHaojian Zhuang * taken in BL31. 3308b167e9SHaojian Zhuang * --------------------------------------------- 3408b167e9SHaojian Zhuang */ 3508b167e9SHaojian Zhuang.macro plat_crash_print_regs 3608b167e9SHaojian Zhuang mov_imm x16, PLAT_ARM_GICD_BASE 3708b167e9SHaojian Zhuang mov_imm x17, PLAT_ARM_GICC_BASE 3808b167e9SHaojian Zhuang 3908b167e9SHaojian Zhuang /* Load the gicc reg list to x6 */ 4008b167e9SHaojian Zhuang adr x6, gicc_regs 4108b167e9SHaojian Zhuang /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 4208b167e9SHaojian Zhuang ldr w8, [x17, #GICC_HPPIR] 4308b167e9SHaojian Zhuang ldr w9, [x17, #GICC_AHPPIR] 4408b167e9SHaojian Zhuang ldr w10, [x17, #GICC_CTLR] 4508b167e9SHaojian Zhuang /* Store to the crash buf and print to cosole */ 4608b167e9SHaojian Zhuang bl str_in_crash_buf_print 4708b167e9SHaojian Zhuang 4808b167e9SHaojian Zhuang /* Print the GICD_ISPENDR regs */ 4908b167e9SHaojian Zhuang add x7, x16, #GICD_ISPENDR 5008b167e9SHaojian Zhuang adr x4, gicd_pend_reg 5108b167e9SHaojian Zhuang bl asm_print_str 5208b167e9SHaojian Zhuang2: 5308b167e9SHaojian Zhuang sub x4, x7, x16 5408b167e9SHaojian Zhuang cmp x4, #0x280 5508b167e9SHaojian Zhuang b.eq 1f 5608b167e9SHaojian Zhuang bl asm_print_hex 5708b167e9SHaojian Zhuang adr x4, spacer 5808b167e9SHaojian Zhuang bl asm_print_str 5908b167e9SHaojian Zhuang ldr x4, [x7], #8 6008b167e9SHaojian Zhuang bl asm_print_hex 6108b167e9SHaojian Zhuang adr x4, newline 6208b167e9SHaojian Zhuang bl asm_print_str 6308b167e9SHaojian Zhuang b 2b 6408b167e9SHaojian Zhuang1: 6508b167e9SHaojian Zhuang adr x6, cci_iface_regs 6608b167e9SHaojian Zhuang /* Store in x7 the base address of the first interface */ 6708b167e9SHaojian Zhuang mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \ 6808b167e9SHaojian Zhuang CCI400_SL_IFACE3_CLUSTER_IX)) 6908b167e9SHaojian Zhuang ldr w8, [x7, #SNOOP_CTRL_REG] 7008b167e9SHaojian Zhuang /* Store in x7 the base address of the second interface */ 7108b167e9SHaojian Zhuang mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \ 7208b167e9SHaojian Zhuang CCI400_SL_IFACE4_CLUSTER_IX)) 7308b167e9SHaojian Zhuang ldr w9, [x7, #SNOOP_CTRL_REG] 7408b167e9SHaojian Zhuang /* Store to the crash buf and print to console */ 7508b167e9SHaojian Zhuang bl str_in_crash_buf_print 7608b167e9SHaojian Zhuang.endm 7708b167e9SHaojian Zhuang 78*c3cf06f1SAntonio Nino Diaz#endif /* PLAT_MACROS_S */ 79