1*08b167e9SHaojian Zhuang/* 2*08b167e9SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*08b167e9SHaojian Zhuang * 4*08b167e9SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5*08b167e9SHaojian Zhuang */ 6*08b167e9SHaojian Zhuang 7*08b167e9SHaojian Zhuang#ifndef __PLAT_MACROS_S__ 8*08b167e9SHaojian Zhuang#define __PLAT_MACROS_S__ 9*08b167e9SHaojian Zhuang 10*08b167e9SHaojian Zhuang#include <cci.h> 11*08b167e9SHaojian Zhuang#include <gic_v2.h> 12*08b167e9SHaojian Zhuang#include <hi6220.h> 13*08b167e9SHaojian Zhuang#include <platform_def.h> 14*08b167e9SHaojian Zhuang 15*08b167e9SHaojian Zhuang.section .rodata.gic_reg_name, "aS" 16*08b167e9SHaojian Zhuanggicc_regs: 17*08b167e9SHaojian Zhuang .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18*08b167e9SHaojian Zhuanggicd_pend_reg: 19*08b167e9SHaojian Zhuang .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 20*08b167e9SHaojian Zhuang " Offset:\t\t\tvalue\n" 21*08b167e9SHaojian Zhuangnewline: 22*08b167e9SHaojian Zhuang .asciz "\n" 23*08b167e9SHaojian Zhuangspacer: 24*08b167e9SHaojian Zhuang .asciz ":\t\t0x" 25*08b167e9SHaojian Zhuang 26*08b167e9SHaojian Zhuang.section .rodata.cci_reg_name, "aS" 27*08b167e9SHaojian Zhuangcci_iface_regs: 28*08b167e9SHaojian Zhuang .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 29*08b167e9SHaojian Zhuang 30*08b167e9SHaojian Zhuang/* --------------------------------------------- 31*08b167e9SHaojian Zhuang * The below macro prints out relevant GIC 32*08b167e9SHaojian Zhuang * registers whenever an unhandled exception is 33*08b167e9SHaojian Zhuang * taken in BL31. 34*08b167e9SHaojian Zhuang * --------------------------------------------- 35*08b167e9SHaojian Zhuang */ 36*08b167e9SHaojian Zhuang.macro plat_crash_print_regs 37*08b167e9SHaojian Zhuang mov_imm x16, PLAT_ARM_GICD_BASE 38*08b167e9SHaojian Zhuang mov_imm x17, PLAT_ARM_GICC_BASE 39*08b167e9SHaojian Zhuang 40*08b167e9SHaojian Zhuang /* Load the gicc reg list to x6 */ 41*08b167e9SHaojian Zhuang adr x6, gicc_regs 42*08b167e9SHaojian Zhuang /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 43*08b167e9SHaojian Zhuang ldr w8, [x17, #GICC_HPPIR] 44*08b167e9SHaojian Zhuang ldr w9, [x17, #GICC_AHPPIR] 45*08b167e9SHaojian Zhuang ldr w10, [x17, #GICC_CTLR] 46*08b167e9SHaojian Zhuang /* Store to the crash buf and print to cosole */ 47*08b167e9SHaojian Zhuang bl str_in_crash_buf_print 48*08b167e9SHaojian Zhuang 49*08b167e9SHaojian Zhuang /* Print the GICD_ISPENDR regs */ 50*08b167e9SHaojian Zhuang add x7, x16, #GICD_ISPENDR 51*08b167e9SHaojian Zhuang adr x4, gicd_pend_reg 52*08b167e9SHaojian Zhuang bl asm_print_str 53*08b167e9SHaojian Zhuang2: 54*08b167e9SHaojian Zhuang sub x4, x7, x16 55*08b167e9SHaojian Zhuang cmp x4, #0x280 56*08b167e9SHaojian Zhuang b.eq 1f 57*08b167e9SHaojian Zhuang bl asm_print_hex 58*08b167e9SHaojian Zhuang adr x4, spacer 59*08b167e9SHaojian Zhuang bl asm_print_str 60*08b167e9SHaojian Zhuang ldr x4, [x7], #8 61*08b167e9SHaojian Zhuang bl asm_print_hex 62*08b167e9SHaojian Zhuang adr x4, newline 63*08b167e9SHaojian Zhuang bl asm_print_str 64*08b167e9SHaojian Zhuang b 2b 65*08b167e9SHaojian Zhuang1: 66*08b167e9SHaojian Zhuang adr x6, cci_iface_regs 67*08b167e9SHaojian Zhuang /* Store in x7 the base address of the first interface */ 68*08b167e9SHaojian Zhuang mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \ 69*08b167e9SHaojian Zhuang CCI400_SL_IFACE3_CLUSTER_IX)) 70*08b167e9SHaojian Zhuang ldr w8, [x7, #SNOOP_CTRL_REG] 71*08b167e9SHaojian Zhuang /* Store in x7 the base address of the second interface */ 72*08b167e9SHaojian Zhuang mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \ 73*08b167e9SHaojian Zhuang CCI400_SL_IFACE4_CLUSTER_IX)) 74*08b167e9SHaojian Zhuang ldr w9, [x7, #SNOOP_CTRL_REG] 75*08b167e9SHaojian Zhuang /* Store to the crash buf and print to console */ 76*08b167e9SHaojian Zhuang bl str_in_crash_buf_print 77*08b167e9SHaojian Zhuang.endm 78*08b167e9SHaojian Zhuang 79*08b167e9SHaojian Zhuang#endif /* __PLAT_MACROS_S__ */ 80