xref: /rk3399_ARM-atf/plat/hisilicon/hikey/include/hisi_ipc.h (revision 127793daba1831044fd0269931c4ea23bc378ab0)
1*127793daSHaojian Zhuang /*
2*127793daSHaojian Zhuang  * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3*127793daSHaojian Zhuang  *
4*127793daSHaojian Zhuang  * SPDX-License-Identifier: BSD-3-Clause
5*127793daSHaojian Zhuang  */
6*127793daSHaojian Zhuang 
7*127793daSHaojian Zhuang #ifndef __HISI_IPC_H__
8*127793daSHaojian Zhuang #define __HISI_IPC_H__
9*127793daSHaojian Zhuang 
10*127793daSHaojian Zhuang #define HISI_IPC_CORE_ACPU		0x0
11*127793daSHaojian Zhuang 
12*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU0_PD	10
13*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU1_PD	11
14*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU2_PD	12
15*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU3_PD	13
16*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU_PD	16
17*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU4_PD	26
18*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU5_PD	27
19*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU6_PD	28
20*127793daSHaojian Zhuang #define HISI_IPC_MCU_INT_SRC_ACPU7_PD	29
21*127793daSHaojian Zhuang 
22*127793daSHaojian Zhuang #define HISI_IPC_SEM_CPUIDLE		27
23*127793daSHaojian Zhuang #define HISI_IPC_INT_SRC_NUM		32
24*127793daSHaojian Zhuang 
25*127793daSHaojian Zhuang #define HISI_IPC_PM_ON			0
26*127793daSHaojian Zhuang #define HISI_IPC_PM_OFF			1
27*127793daSHaojian Zhuang 
28*127793daSHaojian Zhuang #define HISI_IPC_OK			(0)
29*127793daSHaojian Zhuang #define HISI_IPC_ERROR			(-1)
30*127793daSHaojian Zhuang 
31*127793daSHaojian Zhuang #define HISI_IPC_BASE_ADDR		(0xF7510000)
32*127793daSHaojian Zhuang #define HISI_IPC_CPU_RAW_INT_ADDR	(0xF7510420)
33*127793daSHaojian Zhuang #define HISI_IPC_ACPU_CTRL(i)		(0xF7510800 + (i << 3))
34*127793daSHaojian Zhuang 
35*127793daSHaojian Zhuang void hisi_ipc_spin_lock(unsigned int signal);
36*127793daSHaojian Zhuang void hisi_ipc_spin_unlock(unsigned int signal);
37*127793daSHaojian Zhuang void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster);
38*127793daSHaojian Zhuang void hisi_ipc_cpu_off(unsigned int cpu, unsigned int cluster);
39*127793daSHaojian Zhuang void hisi_ipc_cpu_suspend(unsigned int cpu, unsigned int cluster);
40*127793daSHaojian Zhuang void hisi_ipc_cluster_on(unsigned int cpu, unsigned int cluster);
41*127793daSHaojian Zhuang void hisi_ipc_cluster_off(unsigned int cpu, unsigned int cluster);
42*127793daSHaojian Zhuang void hisi_ipc_cluster_suspend(unsigned int cpu, unsigned int cluster);
43*127793daSHaojian Zhuang void hisi_ipc_psci_system_off(void);
44*127793daSHaojian Zhuang int hisi_ipc_init(void);
45*127793daSHaojian Zhuang 
46*127793daSHaojian Zhuang #endif	/* __HISI_IPC_H__ */
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