1*4368ae07SMichael Brandl /* 2*4368ae07SMichael Brandl * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*4368ae07SMichael Brandl * 4*4368ae07SMichael Brandl * SPDX-License-Identifier: BSD-3-Clause 5*4368ae07SMichael Brandl */ 6*4368ae07SMichael Brandl 7*4368ae07SMichael Brandl #ifndef __HIKEY_LAYOUT_H 8*4368ae07SMichael Brandl #define __HIKEY_LAYOUT_H 9*4368ae07SMichael Brandl 10*4368ae07SMichael Brandl /* 11*4368ae07SMichael Brandl * Platform memory map related constants 12*4368ae07SMichael Brandl */ 13*4368ae07SMichael Brandl #define XG2RAM0_BASE 0xF9800000 14*4368ae07SMichael Brandl #define XG2RAM0_SIZE 0x00400000 15*4368ae07SMichael Brandl 16*4368ae07SMichael Brandl /* 17*4368ae07SMichael Brandl * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). 18*4368ae07SMichael Brandl */ 19*4368ae07SMichael Brandl #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) 20*4368ae07SMichael Brandl #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) 21*4368ae07SMichael Brandl #define BL1_XG2RAM0_OFFSET 0x1000 22*4368ae07SMichael Brandl 23*4368ae07SMichael Brandl /* 24*4368ae07SMichael Brandl * BL1 specific defines. 25*4368ae07SMichael Brandl * 26*4368ae07SMichael Brandl * Both loader and BL1_RO region stay in SRAM since they are used to simulate 27*4368ae07SMichael Brandl * ROM. 28*4368ae07SMichael Brandl * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 29*4368ae07SMichael Brandl * 30*4368ae07SMichael Brandl * ++++++++++ 0xF980_0000 31*4368ae07SMichael Brandl * + loader + 32*4368ae07SMichael Brandl * ++++++++++ 0xF980_1000 33*4368ae07SMichael Brandl * + BL1_RO + 34*4368ae07SMichael Brandl * ++++++++++ 0xF981_0000 35*4368ae07SMichael Brandl * + BL1_RW + 36*4368ae07SMichael Brandl * ++++++++++ 0xF989_8000 37*4368ae07SMichael Brandl */ 38*4368ae07SMichael Brandl #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) 39*4368ae07SMichael Brandl #define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000) 40*4368ae07SMichael Brandl #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */ 41*4368ae07SMichael Brandl #define BL1_RW_SIZE (0x00088000) 42*4368ae07SMichael Brandl #define BL1_RW_LIMIT (0xF9898000) 43*4368ae07SMichael Brandl 44*4368ae07SMichael Brandl /* 45*4368ae07SMichael Brandl * Non-Secure BL1U specific defines. 46*4368ae07SMichael Brandl */ 47*4368ae07SMichael Brandl #define NS_BL1U_BASE (0xf9818000) 48*4368ae07SMichael Brandl #define NS_BL1U_SIZE (0x00010000) 49*4368ae07SMichael Brandl #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 50*4368ae07SMichael Brandl 51*4368ae07SMichael Brandl /* 52*4368ae07SMichael Brandl * BL2 specific defines. 53*4368ae07SMichael Brandl * 54*4368ae07SMichael Brandl * Both loader and BL2 region stay in SRAM. 55*4368ae07SMichael Brandl * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 56*4368ae07SMichael Brandl * 57*4368ae07SMichael Brandl * ++++++++++ 0xF980_0000 58*4368ae07SMichael Brandl * + loader + 59*4368ae07SMichael Brandl * ++++++++++ 0xF980_1000 60*4368ae07SMichael Brandl * + BL2 + 61*4368ae07SMichael Brandl * ++++++++++ 0xF981_8000 62*4368ae07SMichael Brandl */ 63*4368ae07SMichael Brandl #define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ 64*4368ae07SMichael Brandl #define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */ 65*4368ae07SMichael Brandl 66*4368ae07SMichael Brandl /* 67*4368ae07SMichael Brandl * SCP_BL2 specific defines. 68*4368ae07SMichael Brandl * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer 69*4368ae07SMichael Brandl * at 0x0100_0000. Then BL2 will parse the sections and loaded them into 70*4368ae07SMichael Brandl * predefined separated buffers. 71*4368ae07SMichael Brandl */ 72*4368ae07SMichael Brandl #define SCP_BL2_BASE (DDR_BASE + 0x01000000) 73*4368ae07SMichael Brandl #define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) 74*4368ae07SMichael Brandl #define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) 75*4368ae07SMichael Brandl 76*4368ae07SMichael Brandl /* 77*4368ae07SMichael Brandl * BL31 specific defines. 78*4368ae07SMichael Brandl */ 79*4368ae07SMichael Brandl #define BL31_BASE (0xF9858000) /* 0xf985_8000 */ 80*4368ae07SMichael Brandl #define BL31_LIMIT (0xF9898000) 81*4368ae07SMichael Brandl 82*4368ae07SMichael Brandl /* 83*4368ae07SMichael Brandl * BL3-2 specific defines. 84*4368ae07SMichael Brandl */ 85*4368ae07SMichael Brandl 86*4368ae07SMichael Brandl /* 87*4368ae07SMichael Brandl * The TSP currently executes from TZC secured area of DRAM or SRAM. 88*4368ae07SMichael Brandl */ 89*4368ae07SMichael Brandl #define BL32_SRAM_BASE BL31_LIMIT 90*4368ae07SMichael Brandl #define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ 91*4368ae07SMichael Brandl 92*4368ae07SMichael Brandl #define BL32_DRAM_BASE DDR_SEC_BASE 93*4368ae07SMichael Brandl #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 94*4368ae07SMichael Brandl 95*4368ae07SMichael Brandl #ifdef SPD_opteed 96*4368ae07SMichael Brandl /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 97*4368ae07SMichael Brandl #define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ 98*4368ae07SMichael Brandl #define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 99*4368ae07SMichael Brandl #endif 100*4368ae07SMichael Brandl 101*4368ae07SMichael Brandl #if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) 102*4368ae07SMichael Brandl #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 103*4368ae07SMichael Brandl #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 104*4368ae07SMichael Brandl #define BL32_BASE BL32_DRAM_BASE 105*4368ae07SMichael Brandl #define BL32_LIMIT BL32_DRAM_LIMIT 106*4368ae07SMichael Brandl #elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) 107*4368ae07SMichael Brandl #define TSP_SEC_MEM_BASE BL32_SRAM_BASE 108*4368ae07SMichael Brandl #define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) 109*4368ae07SMichael Brandl #define BL32_BASE BL32_SRAM_BASE 110*4368ae07SMichael Brandl #define BL32_LIMIT BL32_SRAM_LIMIT 111*4368ae07SMichael Brandl #else 112*4368ae07SMichael Brandl #error "Currently unsupported HIKEY_TSP_LOCATION_ID value" 113*4368ae07SMichael Brandl #endif 114*4368ae07SMichael Brandl 115*4368ae07SMichael Brandl /* BL32 is mandatory in AArch32 */ 116*4368ae07SMichael Brandl #ifndef AARCH32 117*4368ae07SMichael Brandl #ifdef SPD_none 118*4368ae07SMichael Brandl #undef BL32_BASE 119*4368ae07SMichael Brandl #endif /* SPD_none */ 120*4368ae07SMichael Brandl #endif 121*4368ae07SMichael Brandl 122*4368ae07SMichael Brandl #endif /* !__HIKEY_LAYOUT_H */ 123