1*08b167e9SHaojian Zhuang /* 2*08b167e9SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*08b167e9SHaojian Zhuang * 4*08b167e9SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5*08b167e9SHaojian Zhuang */ 6*08b167e9SHaojian Zhuang 7*08b167e9SHaojian Zhuang #ifndef __HI6220_REGS_PMCTRL_H__ 8*08b167e9SHaojian Zhuang #define __HI6220_REGS_PMCTRL_H__ 9*08b167e9SHaojian Zhuang 10*08b167e9SHaojian Zhuang #define PMCTRL_BASE 0xF7032000 11*08b167e9SHaojian Zhuang 12*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLCTRL (PMCTRL_BASE + 0x000) 13*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLFREQ (PMCTRL_BASE + 0x004) 14*08b167e9SHaojian Zhuang #define PMCTRL_DDRPLL1CTRL (PMCTRL_BASE + 0x010) 15*08b167e9SHaojian Zhuang #define PMCTRL_DDRPLL0CTRL (PMCTRL_BASE + 0x030) 16*08b167e9SHaojian Zhuang #define PMCTRL_MEDPLLCTRL (PMCTRL_BASE + 0x038) 17*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLSEL (PMCTRL_BASE + 0x100) 18*08b167e9SHaojian Zhuang #define PMCTRL_ACPUCLKDIV (PMCTRL_BASE + 0x104) 19*08b167e9SHaojian Zhuang #define PMCTRL_ACPUSYSPLLCFG (PMCTRL_BASE + 0x110) 20*08b167e9SHaojian Zhuang #define PMCTRL_ACPUCLKOFFCFG (PMCTRL_BASE + 0x114) 21*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLFRAC (PMCTRL_BASE + 0x134) 22*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPMUVOLUPTIME (PMCTRL_BASE + 0x360) 23*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPMUVOLDNTIME (PMCTRL_BASE + 0x364) 24*08b167e9SHaojian Zhuang #define PMCTRL_ACPUVOLPMUADDR (PMCTRL_BASE + 0x368) 25*08b167e9SHaojian Zhuang #define PMCTRL_ACPUVOLUPSTEP (PMCTRL_BASE + 0x36c) 26*08b167e9SHaojian Zhuang #define PMCTRL_ACPUVOLDNSTEP (PMCTRL_BASE + 0x370) 27*08b167e9SHaojian Zhuang #define PMCTRL_ACPUDFTVOL (PMCTRL_BASE + 0x374) 28*08b167e9SHaojian Zhuang #define PMCTRL_ACPUDESTVOL (PMCTRL_BASE + 0x378) 29*08b167e9SHaojian Zhuang #define PMCTRL_ACPUVOLTTIMEOUT (PMCTRL_BASE + 0x37c) 30*08b167e9SHaojian Zhuang 31*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLCTRL_EN_CFG (1 << 0) 32*08b167e9SHaojian Zhuang 33*08b167e9SHaojian Zhuang #define PMCTRL_ACPUCLKDIV_CPUEXT_CFG_MASK (3 << 0) 34*08b167e9SHaojian Zhuang #define PMCTRL_ACPUCLKDIV_DDR_CFG_MASK (3 << 8) 35*08b167e9SHaojian Zhuang #define PMCTRL_ACPUCLKDIV_CPUEXT_STAT_MASK (3 << 16) 36*08b167e9SHaojian Zhuang #define PMCTRL_ACPUCLKDIV_DDR_STAT_MASK (3 << 24) 37*08b167e9SHaojian Zhuang 38*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLSEL_ACPUPLL_CFG (1 << 0) 39*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLSEL_ACPUPLL_STAT (1 << 1) 40*08b167e9SHaojian Zhuang #define PMCTRL_ACPUPLLSEL_SYSPLL_STAT (1 << 2) 41*08b167e9SHaojian Zhuang 42*08b167e9SHaojian Zhuang #define PMCTRL_ACPUSYSPLL_CLKDIV_CFG_MASK 0x7 43*08b167e9SHaojian Zhuang #define PMCTRL_ACPUSYSPLL_CLKEN_CFG (1 << 4) 44*08b167e9SHaojian Zhuang #define PMCTRL_ACPUSYSPLL_CLKDIV_SW (3 << 12) 45*08b167e9SHaojian Zhuang 46*08b167e9SHaojian Zhuang #define PMCTRL_ACPUSYSPLLCFG_SYSPLL_CLKEN (1 << 4) 47*08b167e9SHaojian Zhuang #define PMCTRL_ACPUSYSPLLCFG_CLKDIV_MASK (3 << 12) 48*08b167e9SHaojian Zhuang 49*08b167e9SHaojian Zhuang #define PMCTRL_ACPUDESTVOL_DEST_VOL_MASK 0x7f 50*08b167e9SHaojian Zhuang #define PMCTRL_ACPUDESTVOL_CURR_VOL_MASK (0x7f << 8) 51*08b167e9SHaojian Zhuang 52*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_START (0) 53*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_en_cfg_END (0) 54*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_START (2) 55*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_rst_END (2) 56*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_START (4) 57*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_time_END (27) 58*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_START (28) 59*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_timeout_END (28) 60*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_START (29) 61*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLCTRL_acpupll_lock_END (29) 62*08b167e9SHaojian Zhuang 63*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLFRAC_ADDR(base) ((base) + (0x134)) 64*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_sw_START (12) 65*08b167e9SHaojian Zhuang 66*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_START (0) 67*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_cfg_END (0) 68*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_START (1) 69*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLSEL_acpu_pllsw_stat_END (1) 70*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_START (2) 71*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUPLLSEL_syspll_sw_stat_END (2) 72*08b167e9SHaojian Zhuang 73*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_START (0) 74*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_cfg_END (1) 75*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_START (8) 76*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_cfg_END (9) 77*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_START (16) 78*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_cpuext_clk_div_stat_END (17) 79*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_START (24) 80*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUCLKDIV_acpu_ddr_clk_div_stat_END (25) 81*08b167e9SHaojian Zhuang 82*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_START (0) 83*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUDESTVOL_acpu_dest_vol_END (6) 84*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_START (8) 85*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUDESTVOL_acpu_vol_using_END (14) 86*08b167e9SHaojian Zhuang 87*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_START (0) 88*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUVOLTIMEOUT_acpu_vol_timeout_END (0) 89*08b167e9SHaojian Zhuang 90*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_START (0) 91*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_cfg_END (2) 92*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_START (4) 93*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_cfg_END (4) 94*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_START (8) 95*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_subsys_clk_div_cfg_END (9) 96*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_START (16) 97*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_div_stat_END (19) 98*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_START (20) 99*08b167e9SHaojian Zhuang #define SOC_PMCTRL_ACPUSYSPLLCFG_acpu_syspll_clken_stat_END (20) 100*08b167e9SHaojian Zhuang 101*08b167e9SHaojian Zhuang #endif /* __HI6220_REGS_PMCTRL_H__ */ 102