1*127793daSHaojian Zhuang/* 2*127793daSHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*127793daSHaojian Zhuang * 4*127793daSHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5*127793daSHaojian Zhuang */ 6*127793daSHaojian Zhuang 7*127793daSHaojian Zhuang#include <arch.h> 8*127793daSHaojian Zhuang#include <asm_macros.S> 9*127793daSHaojian Zhuang#include <cortex_a53.h> 10*127793daSHaojian Zhuang#include <hi6220.h> 11*127793daSHaojian Zhuang#include <hisi_sram_map.h> 12*127793daSHaojian Zhuang 13*127793daSHaojian Zhuang .global pm_asm_code 14*127793daSHaojian Zhuang .global pm_asm_code_end 15*127793daSHaojian Zhuang .global v7_asm 16*127793daSHaojian Zhuang .global v7_asm_end 17*127793daSHaojian Zhuang 18*127793daSHaojian Zhuang .align 3 19*127793daSHaojian Zhuangfunc pm_asm_code 20*127793daSHaojian Zhuang mov x0, 0 21*127793daSHaojian Zhuang msr oslar_el1, x0 22*127793daSHaojian Zhuang 23*127793daSHaojian Zhuang mrs x0, CPUACTLR_EL1 24*127793daSHaojian Zhuang bic x0, x0, #(CPUACTLR_RADIS | CPUACTLR_L1RADIS) 25*127793daSHaojian Zhuang orr x0, x0, #0x180000 26*127793daSHaojian Zhuang orr x0, x0, #0xe000 27*127793daSHaojian Zhuang msr CPUACTLR_EL1, x0 28*127793daSHaojian Zhuang 29*127793daSHaojian Zhuang mrs x3, actlr_el3 30*127793daSHaojian Zhuang orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT 31*127793daSHaojian Zhuang msr actlr_el3, x3 32*127793daSHaojian Zhuang 33*127793daSHaojian Zhuang mrs x3, actlr_el2 34*127793daSHaojian Zhuang orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT 35*127793daSHaojian Zhuang msr actlr_el2, x3 36*127793daSHaojian Zhuang 37*127793daSHaojian Zhuang ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD 38*127793daSHaojian Zhuang mrs x0, mpidr_el1 39*127793daSHaojian Zhuang and x1, x0, #MPIDR_CPU_MASK 40*127793daSHaojian Zhuang and x0, x0, #MPIDR_CLUSTER_MASK 41*127793daSHaojian Zhuang add x0, x1, x0, LSR #6 42*127793daSHaojian Zhuangpen: ldr x4, [x3, x0, LSL #3] 43*127793daSHaojian Zhuang cbz x4, pen 44*127793daSHaojian Zhuang 45*127793daSHaojian Zhuang mov x0, #0x0 46*127793daSHaojian Zhuang mov x1, #0x0 47*127793daSHaojian Zhuang mov x2, #0x0 48*127793daSHaojian Zhuang mov x3, #0x0 49*127793daSHaojian Zhuang br x4 50*127793daSHaojian Zhuang 51*127793daSHaojian Zhuang .ltorg 52*127793daSHaojian Zhuang 53*127793daSHaojian Zhuangpm_asm_code_end: 54*127793daSHaojian Zhuangendfunc pm_asm_code 55*127793daSHaojian Zhuang 56*127793daSHaojian Zhuang /* 57*127793daSHaojian Zhuang * By default, all cores in Hi6220 reset with aarch32 mode. 58*127793daSHaojian Zhuang * Now hardcode ARMv7 instructions to execute warm reset for 59*127793daSHaojian Zhuang * switching aarch64 mode. 60*127793daSHaojian Zhuang */ 61*127793daSHaojian Zhuang .align 3 62*127793daSHaojian Zhuang .section .rodata.v7_asm, "aS" 63*127793daSHaojian Zhuangv7_asm: 64*127793daSHaojian Zhuang .word 0xE1A00000 // nop 65*127793daSHaojian Zhuang .word 0xE3A02003 // mov r2, #3 66*127793daSHaojian Zhuang .word 0xEE0C2F50 // mcr 15, 0, r2, cr12, cr0, {2} 67*127793daSHaojian Zhuang .word 0xE320F003 // wfi 68*127793daSHaojian Zhuang 69*127793daSHaojian Zhuang .ltorg 70*127793daSHaojian Zhuangv7_asm_end: 71