1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <debug.h> 8 #include <mmio.h> 9 #include <hisi_ipc.h> 10 #include <hisi_pwrc.h> 11 #include <hisi_sram_map.h> 12 #include <hi6220_regs_acpu.h> 13 #include <hi6220_regs_ao.h> 14 #include <stdarg.h> 15 #include <stdio.h> 16 #include <string.h> 17 #include <platform_def.h> 18 19 #define CLUSTER_CORE_COUNT (4) 20 #define CLUSTER_CORE_MASK ((1 << CLUSTER_CORE_COUNT) - 1) 21 22 void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster, 23 uintptr_t entry_point) 24 { 25 uintptr_t *core_entry = (uintptr_t *)PWRCTRL_ACPU_ASM_D_ARM_PARA_AD; 26 unsigned int i; 27 28 if (!core_entry) { 29 INFO("%s: core entry point is null!\n", __func__); 30 return; 31 } 32 33 i = cluster * CLUSTER_CORE_COUNT + core; 34 mmio_write_64((uintptr_t)(core_entry + i), entry_point); 35 } 36 37 void hisi_pwrc_set_cluster_wfi(unsigned int cluster) 38 { 39 unsigned int reg = 0; 40 41 if (cluster == 0) { 42 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); 43 reg |= PD_DETECT_START0; 44 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); 45 } else if (cluster == 1) { 46 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); 47 reg |= PD_DETECT_START1; 48 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); 49 } 50 } 51 52 int hisi_pwrc_setup(void) 53 { 54 unsigned int reg, sec_entrypoint; 55 extern char pm_asm_code[], pm_asm_code_end[]; 56 extern char v7_asm[], v7_asm_end[]; 57 58 sec_entrypoint = PWRCTRL_ACPU_ASM_CODE_BASE; 59 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), sec_entrypoint >> 2); 60 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), sec_entrypoint >> 2); 61 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), sec_entrypoint >> 2); 62 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), sec_entrypoint >> 2); 63 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), sec_entrypoint >> 2); 64 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), sec_entrypoint >> 2); 65 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), sec_entrypoint >> 2); 66 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(7), sec_entrypoint >> 2); 67 68 memset((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, 0, 0x400); 69 memcpy((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, (void *)v7_asm, 70 v7_asm_end - v7_asm); 71 72 memcpy((void *)PWRCTRL_ACPU_ASM_CODE_BASE, (void *)pm_asm_code, 73 pm_asm_code_end - pm_asm_code); 74 75 reg = mmio_read_32(AO_SC_SYS_CTRL1); 76 reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM | 77 AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK; 78 mmio_write_32(AO_SC_SYS_CTRL1, reg); 79 80 return 0; 81 } 82