1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <cci.h> 10 #include <debug.h> 11 #include <gicv2.h> 12 #include <hi6220.h> 13 #include <hisi_ipc.h> 14 #include <hisi_pwrc.h> 15 #include <hisi_sram_map.h> 16 #include <mmio.h> 17 #include <psci.h> 18 #include <sp804_delay_timer.h> 19 20 #include "hikey_def.h" 21 22 #define CORE_PWR_STATE(state) \ 23 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 24 #define CLUSTER_PWR_STATE(state) \ 25 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 26 #define SYSTEM_PWR_STATE(state) \ 27 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 28 29 static uintptr_t hikey_sec_entrypoint; 30 31 static int hikey_pwr_domain_on(u_register_t mpidr) 32 { 33 int cpu, cluster; 34 int curr_cluster; 35 36 cluster = MPIDR_AFFLVL1_VAL(mpidr); 37 cpu = MPIDR_AFFLVL0_VAL(mpidr); 38 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); 39 if (cluster != curr_cluster) 40 hisi_ipc_cluster_on(cpu, cluster); 41 42 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 43 hisi_pwrc_enable_debug(cpu, cluster); 44 hisi_ipc_cpu_on(cpu, cluster); 45 46 return 0; 47 } 48 49 static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) 50 { 51 unsigned long mpidr; 52 int cpu, cluster; 53 54 mpidr = read_mpidr(); 55 cluster = MPIDR_AFFLVL1_VAL(mpidr); 56 cpu = MPIDR_AFFLVL0_VAL(mpidr); 57 58 59 /* 60 * Enable CCI coherency for this cluster. 61 * No need for locks as no other cpu is active at the moment. 62 */ 63 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 64 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 65 66 /* Zero the jump address in the mailbox for this cpu */ 67 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 68 69 /* Program the GIC per-cpu distributor or re-distributor interface */ 70 gicv2_pcpu_distif_init(); 71 /* Enable the GIC cpu interface */ 72 gicv2_cpuif_enable(); 73 } 74 75 void hikey_pwr_domain_off(const psci_power_state_t *target_state) 76 { 77 unsigned long mpidr; 78 int cpu, cluster; 79 80 mpidr = read_mpidr(); 81 cluster = MPIDR_AFFLVL1_VAL(mpidr); 82 cpu = MPIDR_AFFLVL0_VAL(mpidr); 83 84 gicv2_cpuif_disable(); 85 hisi_ipc_cpu_off(cpu, cluster); 86 87 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 88 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 89 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 90 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 91 92 hisi_ipc_cluster_off(cpu, cluster); 93 } 94 } 95 96 static void hikey_pwr_domain_suspend(const psci_power_state_t *target_state) 97 { 98 u_register_t mpidr = read_mpidr_el1(); 99 unsigned int cpu = mpidr & MPIDR_CPU_MASK; 100 unsigned int cluster = 101 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; 102 103 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 104 return; 105 106 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 107 108 /* Program the jump address for the target cpu */ 109 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 110 111 gicv2_cpuif_disable(); 112 113 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 114 hisi_ipc_cpu_suspend(cpu, cluster); 115 } 116 117 /* Perform the common cluster specific operations */ 118 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 119 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 120 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 121 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 122 123 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 124 hisi_pwrc_set_cluster_wfi(1); 125 hisi_pwrc_set_cluster_wfi(0); 126 hisi_ipc_psci_system_off(); 127 } else 128 hisi_ipc_cluster_suspend(cpu, cluster); 129 } 130 } 131 132 static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 133 { 134 unsigned long mpidr; 135 unsigned int cluster, cpu; 136 137 /* Nothing to be done on waking up from retention from CPU level */ 138 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 139 return; 140 141 /* Get the mpidr for this cpu */ 142 mpidr = read_mpidr_el1(); 143 cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT; 144 cpu = mpidr & MPIDR_CPU_MASK; 145 146 /* Enable CCI coherency for cluster */ 147 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 148 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 149 150 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 151 152 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 153 gicv2_distif_init(); 154 gicv2_pcpu_distif_init(); 155 gicv2_cpuif_enable(); 156 } else { 157 gicv2_pcpu_distif_init(); 158 gicv2_cpuif_enable(); 159 } 160 } 161 162 static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state) 163 { 164 int i; 165 166 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 167 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 168 } 169 170 static void __dead2 hikey_system_off(void) 171 { 172 NOTICE("%s: off system\n", __func__); 173 174 /* Pull down GPIO_0_0 to trigger PMIC shutdown */ 175 mmio_write_32(0xF8001810, 0x2); /* Pinmux */ 176 mmio_write_8(0xF8011400, 1); /* Pin direction */ 177 mmio_write_8(0xF8011004, 0); /* Pin output value */ 178 179 /* Wait for 2s to power off system by PMIC */ 180 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 181 mdelay(2000); 182 183 /* 184 * PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low, 185 * and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2 186 * through Jumper 1-2. So, to complete shutdown, user needs to manually 187 * remove Jumper 1-2. 188 */ 189 NOTICE("+------------------------------------------+\n"); 190 NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n"); 191 NOTICE("| DANGER: SoC is still burning. DANGER! |\n"); 192 NOTICE("| Board will be reboot to avoid overheat |\n"); 193 NOTICE("+------------------------------------------+\n"); 194 195 /* Send the system reset request */ 196 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 197 198 wfi(); 199 panic(); 200 } 201 202 static void __dead2 hikey_system_reset(void) 203 { 204 /* Send the system reset request */ 205 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 206 isb(); 207 dsb(); 208 209 wfi(); 210 panic(); 211 } 212 213 int hikey_validate_power_state(unsigned int power_state, 214 psci_power_state_t *req_state) 215 { 216 int pstate = psci_get_pstate_type(power_state); 217 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 218 int i; 219 220 assert(req_state); 221 222 if (pwr_lvl > PLAT_MAX_PWR_LVL) 223 return PSCI_E_INVALID_PARAMS; 224 225 /* Sanity check the requested state */ 226 if (pstate == PSTATE_TYPE_STANDBY) { 227 /* 228 * It's possible to enter standby only on power level 0 229 * Ignore any other power level. 230 */ 231 if (pwr_lvl != MPIDR_AFFLVL0) 232 return PSCI_E_INVALID_PARAMS; 233 234 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 235 PLAT_MAX_RET_STATE; 236 } else { 237 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) 238 req_state->pwr_domain_state[i] = 239 PLAT_MAX_OFF_STATE; 240 } 241 242 /* 243 * We expect the 'state id' to be zero. 244 */ 245 if (psci_get_pstate_id(power_state)) 246 return PSCI_E_INVALID_PARAMS; 247 248 return PSCI_E_SUCCESS; 249 } 250 251 static int hikey_validate_ns_entrypoint(uintptr_t entrypoint) 252 { 253 /* 254 * Check if the non secure entrypoint lies within the non 255 * secure DRAM. 256 */ 257 if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE))) 258 return PSCI_E_SUCCESS; 259 260 return PSCI_E_INVALID_ADDRESS; 261 } 262 263 static const plat_psci_ops_t hikey_psci_ops = { 264 .cpu_standby = NULL, 265 .pwr_domain_on = hikey_pwr_domain_on, 266 .pwr_domain_on_finish = hikey_pwr_domain_on_finish, 267 .pwr_domain_off = hikey_pwr_domain_off, 268 .pwr_domain_suspend = hikey_pwr_domain_suspend, 269 .pwr_domain_suspend_finish = hikey_pwr_domain_suspend_finish, 270 .system_off = hikey_system_off, 271 .system_reset = hikey_system_reset, 272 .validate_power_state = hikey_validate_power_state, 273 .validate_ns_entrypoint = hikey_validate_ns_entrypoint, 274 .get_sys_suspend_power_state = hikey_get_sys_suspend_power_state, 275 }; 276 277 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 278 const plat_psci_ops_t **psci_ops) 279 { 280 hikey_sec_entrypoint = sec_entrypoint; 281 282 /* 283 * Initialize PSCI ops struct 284 */ 285 *psci_ops = &hikey_psci_ops; 286 return 0; 287 } 288