1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/arm/cci.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 17 #include <hi6220.h> 18 #include <hikey_def.h> 19 #include <hisi_ipc.h> 20 #include <hisi_pwrc.h> 21 #include <hisi_sram_map.h> 22 23 #define CORE_PWR_STATE(state) \ 24 ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 25 #define CLUSTER_PWR_STATE(state) \ 26 ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 27 #define SYSTEM_PWR_STATE(state) \ 28 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 29 30 static uintptr_t hikey_sec_entrypoint; 31 32 static int hikey_pwr_domain_on(u_register_t mpidr) 33 { 34 int cpu, cluster; 35 int curr_cluster; 36 37 cluster = MPIDR_AFFLVL1_VAL(mpidr); 38 cpu = MPIDR_AFFLVL0_VAL(mpidr); 39 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); 40 if (cluster != curr_cluster) 41 hisi_ipc_cluster_on(cpu, cluster); 42 43 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 44 hisi_pwrc_enable_debug(cpu, cluster); 45 hisi_ipc_cpu_on(cpu, cluster); 46 47 return 0; 48 } 49 50 static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) 51 { 52 unsigned long mpidr; 53 int cpu, cluster; 54 55 mpidr = read_mpidr(); 56 cluster = MPIDR_AFFLVL1_VAL(mpidr); 57 cpu = MPIDR_AFFLVL0_VAL(mpidr); 58 59 60 /* 61 * Enable CCI coherency for this cluster. 62 * No need for locks as no other cpu is active at the moment. 63 */ 64 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 65 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 66 67 /* Zero the jump address in the mailbox for this cpu */ 68 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 69 70 /* Program the GIC per-cpu distributor or re-distributor interface */ 71 gicv2_pcpu_distif_init(); 72 /* Enable the GIC cpu interface */ 73 gicv2_cpuif_enable(); 74 } 75 76 void hikey_pwr_domain_off(const psci_power_state_t *target_state) 77 { 78 unsigned long mpidr; 79 int cpu, cluster; 80 81 mpidr = read_mpidr(); 82 cluster = MPIDR_AFFLVL1_VAL(mpidr); 83 cpu = MPIDR_AFFLVL0_VAL(mpidr); 84 85 gicv2_cpuif_disable(); 86 hisi_ipc_cpu_off(cpu, cluster); 87 88 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 89 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 90 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 91 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 92 93 hisi_ipc_cluster_off(cpu, cluster); 94 } 95 } 96 97 static void hikey_pwr_domain_suspend(const psci_power_state_t *target_state) 98 { 99 u_register_t mpidr = read_mpidr_el1(); 100 unsigned int cpu = mpidr & MPIDR_CPU_MASK; 101 unsigned int cluster = 102 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; 103 104 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 105 return; 106 107 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 108 109 /* Program the jump address for the target cpu */ 110 hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint); 111 112 gicv2_cpuif_disable(); 113 114 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 115 hisi_ipc_cpu_suspend(cpu, cluster); 116 } 117 118 /* Perform the common cluster specific operations */ 119 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 120 hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE); 121 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 122 hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE); 123 124 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 125 hisi_pwrc_set_cluster_wfi(1); 126 hisi_pwrc_set_cluster_wfi(0); 127 hisi_ipc_psci_system_off(); 128 } else 129 hisi_ipc_cluster_suspend(cpu, cluster); 130 } 131 } 132 133 static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 134 { 135 unsigned long mpidr; 136 unsigned int cluster, cpu; 137 138 /* Nothing to be done on waking up from retention from CPU level */ 139 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) 140 return; 141 142 /* Get the mpidr for this cpu */ 143 mpidr = read_mpidr_el1(); 144 cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT; 145 cpu = mpidr & MPIDR_CPU_MASK; 146 147 /* Enable CCI coherency for cluster */ 148 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 149 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); 150 151 hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); 152 153 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 154 gicv2_distif_init(); 155 gicv2_pcpu_distif_init(); 156 gicv2_cpuif_enable(); 157 } else { 158 gicv2_pcpu_distif_init(); 159 gicv2_cpuif_enable(); 160 } 161 } 162 163 static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state) 164 { 165 int i; 166 167 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 168 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 169 } 170 171 static void __dead2 hikey_system_off(void) 172 { 173 NOTICE("%s: off system\n", __func__); 174 175 /* Pull down GPIO_0_0 to trigger PMIC shutdown */ 176 mmio_write_32(0xF8001810, 0x2); /* Pinmux */ 177 mmio_write_8(0xF8011400, 1); /* Pin direction */ 178 mmio_write_8(0xF8011004, 0); /* Pin output value */ 179 180 /* Wait for 2s to power off system by PMIC */ 181 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 182 mdelay(2000); 183 184 /* 185 * PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low, 186 * and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2 187 * through Jumper 1-2. So, to complete shutdown, user needs to manually 188 * remove Jumper 1-2. 189 */ 190 NOTICE("+------------------------------------------+\n"); 191 NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n"); 192 NOTICE("| DANGER: SoC is still burning. DANGER! |\n"); 193 NOTICE("| Board will be reboot to avoid overheat |\n"); 194 NOTICE("+------------------------------------------+\n"); 195 196 /* Send the system reset request */ 197 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 198 199 wfi(); 200 panic(); 201 } 202 203 static void __dead2 hikey_system_reset(void) 204 { 205 /* Send the system reset request */ 206 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284); 207 isb(); 208 dsb(); 209 210 wfi(); 211 panic(); 212 } 213 214 int hikey_validate_power_state(unsigned int power_state, 215 psci_power_state_t *req_state) 216 { 217 int pstate = psci_get_pstate_type(power_state); 218 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 219 int i; 220 221 assert(req_state); 222 223 if (pwr_lvl > PLAT_MAX_PWR_LVL) 224 return PSCI_E_INVALID_PARAMS; 225 226 /* Sanity check the requested state */ 227 if (pstate == PSTATE_TYPE_STANDBY) { 228 /* 229 * It's possible to enter standby only on power level 0 230 * Ignore any other power level. 231 */ 232 if (pwr_lvl != MPIDR_AFFLVL0) 233 return PSCI_E_INVALID_PARAMS; 234 235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = 236 PLAT_MAX_RET_STATE; 237 } else { 238 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) 239 req_state->pwr_domain_state[i] = 240 PLAT_MAX_OFF_STATE; 241 } 242 243 /* 244 * We expect the 'state id' to be zero. 245 */ 246 if (psci_get_pstate_id(power_state)) 247 return PSCI_E_INVALID_PARAMS; 248 249 return PSCI_E_SUCCESS; 250 } 251 252 static int hikey_validate_ns_entrypoint(uintptr_t entrypoint) 253 { 254 /* 255 * Check if the non secure entrypoint lies within the non 256 * secure DRAM. 257 */ 258 if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE))) 259 return PSCI_E_SUCCESS; 260 261 return PSCI_E_INVALID_ADDRESS; 262 } 263 264 static const plat_psci_ops_t hikey_psci_ops = { 265 .cpu_standby = NULL, 266 .pwr_domain_on = hikey_pwr_domain_on, 267 .pwr_domain_on_finish = hikey_pwr_domain_on_finish, 268 .pwr_domain_off = hikey_pwr_domain_off, 269 .pwr_domain_suspend = hikey_pwr_domain_suspend, 270 .pwr_domain_suspend_finish = hikey_pwr_domain_suspend_finish, 271 .system_off = hikey_system_off, 272 .system_reset = hikey_system_reset, 273 .validate_power_state = hikey_validate_power_state, 274 .validate_ns_entrypoint = hikey_validate_ns_entrypoint, 275 .get_sys_suspend_power_state = hikey_get_sys_suspend_power_state, 276 }; 277 278 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 279 const plat_psci_ops_t **psci_ops) 280 { 281 hikey_sec_entrypoint = sec_entrypoint; 282 283 /* 284 * Initialize PSCI ops struct 285 */ 286 *psci_ops = &hikey_psci_ops; 287 return 0; 288 } 289