1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_gic.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cci.h> 12 #include <console.h> 13 #include <debug.h> 14 #include <errno.h> 15 #include <gicv2.h> 16 #include <hi6220.h> 17 #include <hisi_ipc.h> 18 #include <hisi_pwrc.h> 19 #include <platform_def.h> 20 21 #include "hikey_def.h" 22 #include "hikey_private.h" 23 24 /* 25 * The next 2 constants identify the extents of the code & RO data region. 26 * These addresses are used by the MMU setup code and therefore they must be 27 * page-aligned. It is the responsibility of the linker script to ensure that 28 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 29 */ 30 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 31 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 32 33 /* 34 * The next 2 constants identify the extents of the coherent memory region. 35 * These addresses are used by the MMU setup code and therefore they must be 36 * page-aligned. It is the responsibility of the linker script to ensure that 37 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 38 * page-aligned addresses. 39 */ 40 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 41 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 42 43 static entry_point_info_t bl32_ep_info; 44 static entry_point_info_t bl33_ep_info; 45 46 /****************************************************************************** 47 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 48 * interrupts. 49 *****************************************************************************/ 50 const unsigned int g0_interrupt_array[] = { 51 IRQ_SEC_PHY_TIMER, 52 IRQ_SEC_SGI_0 53 }; 54 55 /* 56 * Ideally `arm_gic_data` structure definition should be a `const` but it is 57 * kept as modifiable for overwriting with different GICD and GICC base when 58 * running on FVP with VE memory map. 59 */ 60 gicv2_driver_data_t hikey_gic_data = { 61 .gicd_base = PLAT_ARM_GICD_BASE, 62 .gicc_base = PLAT_ARM_GICC_BASE, 63 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 64 .g0_interrupt_array = g0_interrupt_array, 65 }; 66 67 static const int cci_map[] = { 68 CCI400_SL_IFACE3_CLUSTER_IX, 69 CCI400_SL_IFACE4_CLUSTER_IX 70 }; 71 72 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 73 { 74 entry_point_info_t *next_image_info; 75 76 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 77 78 /* None of the images on this platform can have 0x0 as the entrypoint */ 79 if (next_image_info->pc) 80 return next_image_info; 81 return NULL; 82 } 83 84 #if LOAD_IMAGE_V2 85 void bl31_early_platform_setup(void *from_bl2, 86 void *plat_params_from_bl2) 87 #else 88 void bl31_early_platform_setup(bl31_params_t *from_bl2, 89 void *plat_params_from_bl2) 90 #endif 91 { 92 /* Initialize the console to provide early debug support */ 93 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 94 95 /* Initialize CCI driver */ 96 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 97 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 98 99 #if LOAD_IMAGE_V2 100 /* 101 * Check params passed from BL2 should not be NULL, 102 */ 103 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 104 assert(params_from_bl2 != NULL); 105 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 106 assert(params_from_bl2->h.version >= VERSION_2); 107 108 bl_params_node_t *bl_params = params_from_bl2->head; 109 110 /* 111 * Copy BL33 and BL32 (if present), entry point information. 112 * They are stored in Secure RAM, in BL2's address space. 113 */ 114 while (bl_params) { 115 if (bl_params->image_id == BL32_IMAGE_ID) 116 bl32_ep_info = *bl_params->ep_info; 117 118 if (bl_params->image_id == BL33_IMAGE_ID) 119 bl33_ep_info = *bl_params->ep_info; 120 121 bl_params = bl_params->next_params_info; 122 } 123 124 if (bl33_ep_info.pc == 0) 125 panic(); 126 127 #else /* LOAD_IMAGE_V2 */ 128 129 /* 130 * Check params passed from BL2 should not be NULL, 131 */ 132 assert(from_bl2 != NULL); 133 assert(from_bl2->h.type == PARAM_BL31); 134 assert(from_bl2->h.version >= VERSION_1); 135 136 /* 137 * Copy BL3-2 and BL3-3 entry point information. 138 * They are stored in Secure RAM, in BL2's address space. 139 */ 140 bl32_ep_info = *from_bl2->bl32_ep_info; 141 bl33_ep_info = *from_bl2->bl33_ep_info; 142 #endif /* LOAD_IMAGE_V2 */ 143 } 144 145 void bl31_plat_arch_setup(void) 146 { 147 hikey_init_mmu_el3(BL31_BASE, 148 BL31_LIMIT - BL31_BASE, 149 BL31_RO_BASE, 150 BL31_RO_LIMIT, 151 BL31_COHERENT_RAM_BASE, 152 BL31_COHERENT_RAM_LIMIT); 153 } 154 155 void bl31_platform_setup(void) 156 { 157 /* Initialize the GIC driver, cpu and distributor interfaces */ 158 gicv2_driver_init(&hikey_gic_data); 159 gicv2_distif_init(); 160 gicv2_pcpu_distif_init(); 161 gicv2_cpuif_enable(); 162 163 hisi_ipc_init(); 164 hisi_pwrc_setup(); 165 } 166 167 void bl31_plat_runtime_setup(void) 168 { 169 } 170