1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_gic.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <errno.h> 14 #include <gicv2.h> 15 #include <hi6220.h> 16 #include <hisi_ipc.h> 17 #include <hisi_pwrc.h> 18 #include <platform_def.h> 19 20 #include "hikey_def.h" 21 #include "hikey_private.h" 22 23 /* 24 * The next 2 constants identify the extents of the code & RO data region. 25 * These addresses are used by the MMU setup code and therefore they must be 26 * page-aligned. It is the responsibility of the linker script to ensure that 27 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 28 */ 29 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 30 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 31 32 /* 33 * The next 2 constants identify the extents of the coherent memory region. 34 * These addresses are used by the MMU setup code and therefore they must be 35 * page-aligned. It is the responsibility of the linker script to ensure that 36 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 37 * page-aligned addresses. 38 */ 39 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 40 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 41 42 static entry_point_info_t bl32_ep_info; 43 static entry_point_info_t bl33_ep_info; 44 45 /****************************************************************************** 46 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 47 * interrupts. 48 *****************************************************************************/ 49 const unsigned int g0_interrupt_array[] = { 50 IRQ_SEC_PHY_TIMER, 51 IRQ_SEC_SGI_0 52 }; 53 54 /* 55 * Ideally `arm_gic_data` structure definition should be a `const` but it is 56 * kept as modifiable for overwriting with different GICD and GICC base when 57 * running on FVP with VE memory map. 58 */ 59 gicv2_driver_data_t hikey_gic_data = { 60 .gicd_base = PLAT_ARM_GICD_BASE, 61 .gicc_base = PLAT_ARM_GICC_BASE, 62 .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), 63 .g0_interrupt_array = g0_interrupt_array, 64 }; 65 66 static const int cci_map[] = { 67 CCI400_SL_IFACE3_CLUSTER_IX, 68 CCI400_SL_IFACE4_CLUSTER_IX 69 }; 70 71 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 72 { 73 entry_point_info_t *next_image_info; 74 75 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 76 77 /* None of the images on this platform can have 0x0 as the entrypoint */ 78 if (next_image_info->pc) 79 return next_image_info; 80 return NULL; 81 } 82 83 void bl31_early_platform_setup(bl31_params_t *from_bl2, 84 void *plat_params_from_bl2) 85 { 86 /* Initialize the console to provide early debug support */ 87 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 88 89 /* Initialize CCI driver */ 90 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 91 92 /* 93 * Copy BL3-2 and BL3-3 entry point information. 94 * They are stored in Secure RAM, in BL2's address space. 95 */ 96 bl32_ep_info = *from_bl2->bl32_ep_info; 97 bl33_ep_info = *from_bl2->bl33_ep_info; 98 } 99 100 void bl31_plat_arch_setup(void) 101 { 102 hikey_init_mmu_el3(BL31_BASE, 103 BL31_LIMIT - BL31_BASE, 104 BL31_RO_BASE, 105 BL31_RO_LIMIT, 106 BL31_COHERENT_RAM_BASE, 107 BL31_COHERENT_RAM_LIMIT); 108 } 109 110 void bl31_platform_setup(void) 111 { 112 /* Initialize the GIC driver, cpu and distributor interfaces */ 113 gicv2_driver_init(&hikey_gic_data); 114 gicv2_distif_init(); 115 gicv2_pcpu_distif_init(); 116 gicv2_cpuif_enable(); 117 118 hisi_ipc_init(); 119 hisi_pwrc_setup(); 120 } 121 122 void bl31_plat_runtime_setup(void) 123 { 124 } 125