1 /* 2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/interrupt_props.h> 16 #include <drivers/arm/cci.h> 17 #include <drivers/arm/gicv2.h> 18 #include <drivers/arm/pl011.h> 19 #include <lib/mmio.h> 20 21 #include <hi6220.h> 22 #include <hikey_def.h> 23 #include <hisi_ipc.h> 24 #include <hisi_pwrc.h> 25 26 #include "hikey_private.h" 27 28 static entry_point_info_t bl32_ep_info; 29 static entry_point_info_t bl33_ep_info; 30 static console_t console; 31 32 /****************************************************************************** 33 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 34 * interrupts. 35 *****************************************************************************/ 36 static const interrupt_prop_t g0_interrupt_props[] = { 37 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 38 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 39 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 41 }; 42 43 /* 44 * Ideally `arm_gic_data` structure definition should be a `const` but it is 45 * kept as modifiable for overwriting with different GICD and GICC base when 46 * running on FVP with VE memory map. 47 */ 48 gicv2_driver_data_t hikey_gic_data = { 49 .gicd_base = PLAT_ARM_GICD_BASE, 50 .gicc_base = PLAT_ARM_GICC_BASE, 51 .interrupt_props = g0_interrupt_props, 52 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 53 }; 54 55 static const int cci_map[] = { 56 CCI400_SL_IFACE3_CLUSTER_IX, 57 CCI400_SL_IFACE4_CLUSTER_IX 58 }; 59 60 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 61 { 62 entry_point_info_t *next_image_info; 63 64 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 65 66 /* None of the images on this platform can have 0x0 as the entrypoint */ 67 if (next_image_info->pc) 68 return next_image_info; 69 return NULL; 70 } 71 72 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 73 u_register_t arg2, u_register_t arg3) 74 { 75 void *from_bl2; 76 77 from_bl2 = (void *) arg0; 78 79 /* Initialize the console to provide early debug support */ 80 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 81 PL011_BAUDRATE, &console); 82 83 /* Initialize CCI driver */ 84 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 85 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 86 87 /* 88 * Check params passed from BL2 should not be NULL, 89 */ 90 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 91 assert(params_from_bl2 != NULL); 92 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 93 assert(params_from_bl2->h.version >= VERSION_2); 94 95 bl_params_node_t *bl_params = params_from_bl2->head; 96 97 /* 98 * Copy BL33 and BL32 (if present), entry point information. 99 * They are stored in Secure RAM, in BL2's address space. 100 */ 101 while (bl_params) { 102 if (bl_params->image_id == BL32_IMAGE_ID) 103 bl32_ep_info = *bl_params->ep_info; 104 105 if (bl_params->image_id == BL33_IMAGE_ID) 106 bl33_ep_info = *bl_params->ep_info; 107 108 bl_params = bl_params->next_params_info; 109 } 110 111 if (bl33_ep_info.pc == 0) 112 panic(); 113 } 114 115 void bl31_plat_arch_setup(void) 116 { 117 hikey_init_mmu_el3(BL31_BASE, 118 BL31_LIMIT - BL31_BASE, 119 BL_CODE_BASE, 120 BL_CODE_END, 121 BL_COHERENT_RAM_BASE, 122 BL_COHERENT_RAM_END); 123 } 124 125 /* Initialize EDMAC controller with non-secure mode. */ 126 static void hikey_edma_init(void) 127 { 128 int i; 129 uint32_t non_secure; 130 131 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 132 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 133 134 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) { 135 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 136 } 137 } 138 139 void bl31_platform_setup(void) 140 { 141 /* Initialize the GIC driver, cpu and distributor interfaces */ 142 gicv2_driver_init(&hikey_gic_data); 143 gicv2_distif_init(); 144 gicv2_pcpu_distif_init(); 145 gicv2_cpuif_enable(); 146 147 hikey_edma_init(); 148 149 hisi_ipc_init(); 150 hisi_pwrc_setup(); 151 } 152