1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/synopsys/dw_mmc.h> 21 #include <lib/mmio.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <plat/common/platform.h> 26 27 #include <hi6220.h> 28 #include <hisi_mcu.h> 29 #include <hisi_sram_map.h> 30 #include "hikey_private.h" 31 32 #define BL2_RW_BASE (BL_CODE_END) 33 34 static meminfo_t bl2_el3_tzram_layout; 35 static console_pl011_t console; 36 37 enum { 38 BOOT_MODE_RECOVERY = 0, 39 BOOT_MODE_NORMAL, 40 BOOT_MODE_MASK = 1, 41 }; 42 43 /******************************************************************************* 44 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 45 * Return 0 on success, -1 otherwise. 46 ******************************************************************************/ 47 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 48 { 49 /* Enable MCU SRAM */ 50 hisi_mcu_enable_sram(); 51 52 /* Load MCU binary into SRAM */ 53 hisi_mcu_load_image(scp_bl2_image_info->image_base, 54 scp_bl2_image_info->image_size); 55 /* Let MCU running */ 56 hisi_mcu_start_run(); 57 58 INFO("%s: MCU PC is at 0x%x\n", 59 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 60 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 61 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 62 return 0; 63 } 64 65 /******************************************************************************* 66 * Gets SPSR for BL32 entry 67 ******************************************************************************/ 68 uint32_t hikey_get_spsr_for_bl32_entry(void) 69 { 70 /* 71 * The Secure Payload Dispatcher service is responsible for 72 * setting the SPSR prior to entry into the BL3-2 image. 73 */ 74 return 0; 75 } 76 77 /******************************************************************************* 78 * Gets SPSR for BL33 entry 79 ******************************************************************************/ 80 #ifndef AARCH32 81 uint32_t hikey_get_spsr_for_bl33_entry(void) 82 { 83 unsigned int mode; 84 uint32_t spsr; 85 86 /* Figure out what mode we enter the non-secure world in */ 87 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 88 89 /* 90 * TODO: Consider the possibility of specifying the SPSR in 91 * the FIP ToC and allowing the platform to have a say as 92 * well. 93 */ 94 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 95 return spsr; 96 } 97 #else 98 uint32_t hikey_get_spsr_for_bl33_entry(void) 99 { 100 unsigned int hyp_status, mode, spsr; 101 102 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 103 104 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 105 106 /* 107 * TODO: Consider the possibility of specifying the SPSR in 108 * the FIP ToC and allowing the platform to have a say as 109 * well. 110 */ 111 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 112 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 113 return spsr; 114 } 115 #endif /* AARCH32 */ 116 117 int hikey_bl2_handle_post_image_load(unsigned int image_id) 118 { 119 int err = 0; 120 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 121 #ifdef SPD_opteed 122 bl_mem_params_node_t *pager_mem_params = NULL; 123 bl_mem_params_node_t *paged_mem_params = NULL; 124 #endif 125 assert(bl_mem_params); 126 127 switch (image_id) { 128 #ifdef AARCH64 129 case BL32_IMAGE_ID: 130 #ifdef SPD_opteed 131 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 132 assert(pager_mem_params); 133 134 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 135 assert(paged_mem_params); 136 137 err = parse_optee_header(&bl_mem_params->ep_info, 138 &pager_mem_params->image_info, 139 &paged_mem_params->image_info); 140 if (err != 0) { 141 WARN("OPTEE header parse error.\n"); 142 } 143 #endif 144 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); 145 break; 146 #endif 147 148 case BL33_IMAGE_ID: 149 /* BL33 expects to receive the primary CPU MPID (through r0) */ 150 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 151 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); 152 break; 153 154 #ifdef SCP_BL2_BASE 155 case SCP_BL2_IMAGE_ID: 156 /* The subsequent handling of SCP_BL2 is platform specific */ 157 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info); 158 if (err) { 159 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 160 } 161 break; 162 #endif 163 default: 164 /* Do nothing in default case */ 165 break; 166 } 167 168 return err; 169 } 170 171 /******************************************************************************* 172 * This function can be used by the platforms to update/use image 173 * information for given `image_id`. 174 ******************************************************************************/ 175 int bl2_plat_handle_post_image_load(unsigned int image_id) 176 { 177 return hikey_bl2_handle_post_image_load(image_id); 178 } 179 180 static void reset_dwmmc_clk(void) 181 { 182 unsigned int data; 183 184 /* disable mmc0 bus clock */ 185 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 186 do { 187 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 188 } while (data & PERI_CLK0_MMC0); 189 /* enable mmc0 bus clock */ 190 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 191 do { 192 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 193 } while (!(data & PERI_CLK0_MMC0)); 194 /* reset mmc0 clock domain */ 195 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 196 197 /* bypass mmc0 clock phase */ 198 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 199 data |= 3; 200 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 201 202 /* disable low power */ 203 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 204 data |= 1 << 3; 205 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 206 do { 207 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 208 } while (!(data & PERI_RST0_MMC0)); 209 210 /* unreset mmc0 clock domain */ 211 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 212 do { 213 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 214 } while (data & PERI_RST0_MMC0); 215 } 216 217 static void hikey_boardid_init(void) 218 { 219 u_register_t midr; 220 221 midr = read_midr(); 222 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 223 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 224 (unsigned int)midr); 225 226 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 227 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 228 229 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 230 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 231 } 232 233 static void hikey_sd_init(void) 234 { 235 /* switch pinmux to SD */ 236 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 237 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 238 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 239 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 240 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 241 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 242 243 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 244 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 245 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 246 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 247 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 248 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 249 250 /* set SD Card detect as nopull */ 251 mmio_write_32(IOCG_GPIO8, 0); 252 } 253 254 static void hikey_jumper_init(void) 255 { 256 /* set jumper detect as nopull */ 257 mmio_write_32(IOCG_GPIO24, 0); 258 /* set jumper detect as GPIO */ 259 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 260 } 261 262 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 263 u_register_t arg3, u_register_t arg4) 264 { 265 /* Initialize the console to provide early debug support */ 266 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 267 PL011_BAUDRATE, &console); 268 /* 269 * Allow BL2 to see the whole Trusted RAM. 270 */ 271 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 272 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 273 } 274 275 void bl2_el3_plat_arch_setup(void) 276 { 277 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base, 278 bl2_el3_tzram_layout.total_size, 279 BL_CODE_BASE, 280 BL_CODE_END, 281 BL_COHERENT_RAM_BASE, 282 BL_COHERENT_RAM_END); 283 } 284 285 void bl2_platform_setup(void) 286 { 287 dw_mmc_params_t params; 288 struct mmc_device_info info; 289 290 hikey_sp804_init(); 291 hikey_gpio_init(); 292 hikey_pmussi_init(); 293 hikey_hi6553_init(); 294 /* Clear SRAM since it'll be used by MCU right now. */ 295 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 296 297 dsb(); 298 hikey_ddr_init(DDR_FREQ_800M); 299 hikey_security_setup(); 300 301 hikey_boardid_init(); 302 init_acpu_dvfs(); 303 hikey_rtc_init(); 304 hikey_sd_init(); 305 hikey_jumper_init(); 306 307 hikey_mmc_pll_init(); 308 309 /* Clean SRAM before MCU used */ 310 clean_dcache_range(SRAM_BASE, SRAM_SIZE); 311 312 reset_dwmmc_clk(); 313 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 314 params.reg_base = DWMMC0_BASE; 315 params.desc_base = HIKEY_MMC_DESC_BASE; 316 params.desc_size = 1 << 20; 317 params.clk_rate = 24 * 1000 * 1000; 318 params.bus_width = MMC_BUS_WIDTH_8; 319 params.flags = MMC_FLAG_CMD23; 320 info.mmc_dev_type = MMC_IS_EMMC; 321 dw_mmc_init(¶ms, &info); 322 323 hikey_io_setup(); 324 } 325