1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/synopsys/dw_mmc.h> 21 #include <lib/mmio.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <plat/common/platform.h> 26 27 #include <hi6220.h> 28 #include <hisi_mcu.h> 29 #include <hisi_sram_map.h> 30 #include "hikey_private.h" 31 32 /* 33 * The next 2 constants identify the extents of the code & RO data region. 34 * These addresses are used by the MMU setup code and therefore they must be 35 * page-aligned. It is the responsibility of the linker script to ensure that 36 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 37 */ 38 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 39 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 40 41 #define BL2_RW_BASE (BL2_RO_LIMIT) 42 43 /* 44 * The next 2 constants identify the extents of the coherent memory region. 45 * These addresses are used by the MMU setup code and therefore they must be 46 * page-aligned. It is the responsibility of the linker script to ensure that 47 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 48 * page-aligned addresses. 49 */ 50 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 51 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 52 53 static meminfo_t bl2_el3_tzram_layout; 54 static console_pl011_t console; 55 56 enum { 57 BOOT_MODE_RECOVERY = 0, 58 BOOT_MODE_NORMAL, 59 BOOT_MODE_MASK = 1, 60 }; 61 62 /******************************************************************************* 63 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 64 * Return 0 on success, -1 otherwise. 65 ******************************************************************************/ 66 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 67 { 68 /* Enable MCU SRAM */ 69 hisi_mcu_enable_sram(); 70 71 /* Load MCU binary into SRAM */ 72 hisi_mcu_load_image(scp_bl2_image_info->image_base, 73 scp_bl2_image_info->image_size); 74 /* Let MCU running */ 75 hisi_mcu_start_run(); 76 77 INFO("%s: MCU PC is at 0x%x\n", 78 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 79 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 80 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 81 return 0; 82 } 83 84 /******************************************************************************* 85 * Gets SPSR for BL32 entry 86 ******************************************************************************/ 87 uint32_t hikey_get_spsr_for_bl32_entry(void) 88 { 89 /* 90 * The Secure Payload Dispatcher service is responsible for 91 * setting the SPSR prior to entry into the BL3-2 image. 92 */ 93 return 0; 94 } 95 96 /******************************************************************************* 97 * Gets SPSR for BL33 entry 98 ******************************************************************************/ 99 #ifndef AARCH32 100 uint32_t hikey_get_spsr_for_bl33_entry(void) 101 { 102 unsigned int mode; 103 uint32_t spsr; 104 105 /* Figure out what mode we enter the non-secure world in */ 106 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 107 108 /* 109 * TODO: Consider the possibility of specifying the SPSR in 110 * the FIP ToC and allowing the platform to have a say as 111 * well. 112 */ 113 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 114 return spsr; 115 } 116 #else 117 uint32_t hikey_get_spsr_for_bl33_entry(void) 118 { 119 unsigned int hyp_status, mode, spsr; 120 121 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 122 123 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 124 125 /* 126 * TODO: Consider the possibility of specifying the SPSR in 127 * the FIP ToC and allowing the platform to have a say as 128 * well. 129 */ 130 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 131 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 132 return spsr; 133 } 134 #endif /* AARCH32 */ 135 136 int hikey_bl2_handle_post_image_load(unsigned int image_id) 137 { 138 int err = 0; 139 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 140 #ifdef SPD_opteed 141 bl_mem_params_node_t *pager_mem_params = NULL; 142 bl_mem_params_node_t *paged_mem_params = NULL; 143 #endif 144 assert(bl_mem_params); 145 146 switch (image_id) { 147 #ifdef AARCH64 148 case BL32_IMAGE_ID: 149 #ifdef SPD_opteed 150 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 151 assert(pager_mem_params); 152 153 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 154 assert(paged_mem_params); 155 156 err = parse_optee_header(&bl_mem_params->ep_info, 157 &pager_mem_params->image_info, 158 &paged_mem_params->image_info); 159 if (err != 0) { 160 WARN("OPTEE header parse error.\n"); 161 } 162 #endif 163 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); 164 break; 165 #endif 166 167 case BL33_IMAGE_ID: 168 /* BL33 expects to receive the primary CPU MPID (through r0) */ 169 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 170 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); 171 break; 172 173 #ifdef SCP_BL2_BASE 174 case SCP_BL2_IMAGE_ID: 175 /* The subsequent handling of SCP_BL2 is platform specific */ 176 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info); 177 if (err) { 178 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 179 } 180 break; 181 #endif 182 default: 183 /* Do nothing in default case */ 184 break; 185 } 186 187 return err; 188 } 189 190 /******************************************************************************* 191 * This function can be used by the platforms to update/use image 192 * information for given `image_id`. 193 ******************************************************************************/ 194 int bl2_plat_handle_post_image_load(unsigned int image_id) 195 { 196 return hikey_bl2_handle_post_image_load(image_id); 197 } 198 199 static void reset_dwmmc_clk(void) 200 { 201 unsigned int data; 202 203 /* disable mmc0 bus clock */ 204 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 205 do { 206 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 207 } while (data & PERI_CLK0_MMC0); 208 /* enable mmc0 bus clock */ 209 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 210 do { 211 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 212 } while (!(data & PERI_CLK0_MMC0)); 213 /* reset mmc0 clock domain */ 214 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 215 216 /* bypass mmc0 clock phase */ 217 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 218 data |= 3; 219 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 220 221 /* disable low power */ 222 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 223 data |= 1 << 3; 224 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 225 do { 226 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 227 } while (!(data & PERI_RST0_MMC0)); 228 229 /* unreset mmc0 clock domain */ 230 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 231 do { 232 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 233 } while (data & PERI_RST0_MMC0); 234 } 235 236 static void hikey_boardid_init(void) 237 { 238 u_register_t midr; 239 240 midr = read_midr(); 241 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 242 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 243 (unsigned int)midr); 244 245 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 246 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 247 248 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 249 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 250 } 251 252 static void hikey_sd_init(void) 253 { 254 /* switch pinmux to SD */ 255 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 256 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 257 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 258 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 259 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 260 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 261 262 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 263 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 264 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 265 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 266 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 267 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 268 269 /* set SD Card detect as nopull */ 270 mmio_write_32(IOCG_GPIO8, 0); 271 } 272 273 static void hikey_jumper_init(void) 274 { 275 /* set jumper detect as nopull */ 276 mmio_write_32(IOCG_GPIO24, 0); 277 /* set jumper detect as GPIO */ 278 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 279 } 280 281 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 282 u_register_t arg3, u_register_t arg4) 283 { 284 /* Initialize the console to provide early debug support */ 285 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 286 PL011_BAUDRATE, &console); 287 /* 288 * Allow BL2 to see the whole Trusted RAM. 289 */ 290 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 291 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 292 } 293 294 void bl2_el3_plat_arch_setup(void) 295 { 296 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base, 297 bl2_el3_tzram_layout.total_size, 298 BL2_RO_BASE, 299 BL2_RO_LIMIT, 300 BL2_COHERENT_RAM_BASE, 301 BL2_COHERENT_RAM_LIMIT); 302 } 303 304 void bl2_platform_setup(void) 305 { 306 dw_mmc_params_t params; 307 struct mmc_device_info info; 308 309 hikey_sp804_init(); 310 hikey_gpio_init(); 311 hikey_pmussi_init(); 312 hikey_hi6553_init(); 313 /* Clear SRAM since it'll be used by MCU right now. */ 314 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 315 316 dsb(); 317 hikey_ddr_init(DDR_FREQ_800M); 318 hikey_security_setup(); 319 320 hikey_boardid_init(); 321 init_acpu_dvfs(); 322 hikey_rtc_init(); 323 hikey_sd_init(); 324 hikey_jumper_init(); 325 326 hikey_mmc_pll_init(); 327 328 /* Clean SRAM before MCU used */ 329 clean_dcache_range(SRAM_BASE, SRAM_SIZE); 330 331 reset_dwmmc_clk(); 332 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 333 params.reg_base = DWMMC0_BASE; 334 params.desc_base = HIKEY_MMC_DESC_BASE; 335 params.desc_size = 1 << 20; 336 params.clk_rate = 24 * 1000 * 1000; 337 params.bus_width = MMC_BUS_WIDTH_8; 338 params.flags = MMC_FLAG_CMD23; 339 info.mmc_dev_type = MMC_IS_EMMC; 340 dw_mmc_init(¶ms, &info); 341 342 hikey_io_setup(); 343 } 344