1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <emmc.h> 14 #include <errno.h> 15 #include <hi6220.h> 16 #include <hisi_mcu.h> 17 #include <hisi_sram_map.h> 18 #include <mmio.h> 19 #include <platform_def.h> 20 #include <sp804_delay_timer.h> 21 #include <string.h> 22 23 #include "hikey_def.h" 24 #include "hikey_private.h" 25 26 /* 27 * The next 2 constants identify the extents of the code & RO data region. 28 * These addresses are used by the MMU setup code and therefore they must be 29 * page-aligned. It is the responsibility of the linker script to ensure that 30 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 31 */ 32 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 33 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 34 35 /* 36 * The next 2 constants identify the extents of the coherent memory region. 37 * These addresses are used by the MMU setup code and therefore they must be 38 * page-aligned. It is the responsibility of the linker script to ensure that 39 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 40 * page-aligned addresses. 41 */ 42 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 43 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 44 45 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 46 47 typedef struct bl2_to_bl31_params_mem { 48 bl31_params_t bl31_params; 49 image_info_t bl31_image_info; 50 image_info_t bl32_image_info; 51 image_info_t bl33_image_info; 52 entry_point_info_t bl33_ep_info; 53 entry_point_info_t bl32_ep_info; 54 entry_point_info_t bl31_ep_info; 55 } bl2_to_bl31_params_mem_t; 56 57 static bl2_to_bl31_params_mem_t bl31_params_mem; 58 59 meminfo_t *bl2_plat_sec_mem_layout(void) 60 { 61 return &bl2_tzram_layout; 62 } 63 64 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 65 { 66 scp_bl2_meminfo->total_base = SCP_BL2_BASE; 67 scp_bl2_meminfo->total_size = SCP_BL2_SIZE; 68 scp_bl2_meminfo->free_base = SCP_BL2_BASE; 69 scp_bl2_meminfo->free_size = SCP_BL2_SIZE; 70 } 71 72 int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) 73 { 74 /* Enable MCU SRAM */ 75 hisi_mcu_enable_sram(); 76 77 /* Load MCU binary into SRAM */ 78 hisi_mcu_load_image(scp_bl2_image_info->image_base, 79 scp_bl2_image_info->image_size); 80 /* Let MCU running */ 81 hisi_mcu_start_run(); 82 83 INFO("%s: MCU PC is at 0x%x\n", 84 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 85 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 86 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 87 return 0; 88 } 89 90 bl31_params_t *bl2_plat_get_bl31_params(void) 91 { 92 bl31_params_t *bl2_to_bl31_params = NULL; 93 94 /* 95 * Initialise the memory for all the arguments that needs to 96 * be passed to BL3-1 97 */ 98 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 99 100 /* Assign memory for TF related information */ 101 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 102 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 103 104 /* Fill BL3-1 related information */ 105 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 106 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 107 VERSION_1, 0); 108 109 /* Fill BL3-2 related information if it exists */ 110 #if BL32_BASE 111 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 112 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 113 VERSION_1, 0); 114 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 115 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 116 VERSION_1, 0); 117 #endif 118 119 /* Fill BL3-3 related information */ 120 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 121 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 122 PARAM_EP, VERSION_1, 0); 123 124 /* BL3-3 expects to receive the primary CPU MPID (through x0) */ 125 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 126 127 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 128 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 129 VERSION_1, 0); 130 131 return bl2_to_bl31_params; 132 } 133 134 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 135 { 136 return &bl31_params_mem.bl31_ep_info; 137 } 138 139 void bl2_plat_set_bl31_ep_info(image_info_t *image, 140 entry_point_info_t *bl31_ep_info) 141 { 142 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 143 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 144 DISABLE_ALL_EXCEPTIONS); 145 } 146 147 /******************************************************************************* 148 * Before calling this function BL32 is loaded in memory and its entrypoint 149 * is set by load_image. This is a placeholder for the platform to change 150 * the entrypoint of BL32 and set SPSR and security state. 151 * On Hikey we only set the security state of the entrypoint 152 ******************************************************************************/ 153 #ifdef BL32_BASE 154 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 155 entry_point_info_t *bl32_ep_info) 156 { 157 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 158 /* 159 * The Secure Payload Dispatcher service is responsible for 160 * setting the SPSR prior to entry into the BL32 image. 161 */ 162 bl32_ep_info->spsr = 0; 163 } 164 165 /******************************************************************************* 166 * Populate the extents of memory available for loading BL32 167 ******************************************************************************/ 168 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 169 { 170 /* 171 * Populate the extents of memory available for loading BL32. 172 */ 173 bl32_meminfo->total_base = BL32_BASE; 174 bl32_meminfo->free_base = BL32_BASE; 175 bl32_meminfo->total_size = 176 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 177 bl32_meminfo->free_size = 178 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 179 } 180 #endif /* BL32_BASE */ 181 182 void bl2_plat_set_bl33_ep_info(image_info_t *image, 183 entry_point_info_t *bl33_ep_info) 184 { 185 unsigned long el_status; 186 unsigned int mode; 187 188 /* Figure out what mode we enter the non-secure world in */ 189 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 190 el_status &= ID_AA64PFR0_ELX_MASK; 191 192 if (el_status) 193 mode = MODE_EL2; 194 else 195 mode = MODE_EL1; 196 197 /* 198 * TODO: Consider the possibility of specifying the SPSR in 199 * the FIP ToC and allowing the platform to have a say as 200 * well. 201 */ 202 bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, 203 DISABLE_ALL_EXCEPTIONS); 204 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 205 } 206 207 void bl2_plat_flush_bl31_params(void) 208 { 209 flush_dcache_range((unsigned long)&bl31_params_mem, 210 sizeof(bl2_to_bl31_params_mem_t)); 211 } 212 213 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 214 { 215 bl33_meminfo->total_base = DDR_BASE; 216 bl33_meminfo->total_size = DDR_SIZE; 217 bl33_meminfo->free_base = DDR_BASE; 218 bl33_meminfo->free_size = DDR_SIZE; 219 } 220 221 static void reset_dwmmc_clk(void) 222 { 223 unsigned int data; 224 225 /* disable mmc0 bus clock */ 226 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 227 do { 228 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 229 } while (data & PERI_CLK0_MMC0); 230 /* enable mmc0 bus clock */ 231 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 232 do { 233 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 234 } while (!(data & PERI_CLK0_MMC0)); 235 /* reset mmc0 clock domain */ 236 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 237 238 /* bypass mmc0 clock phase */ 239 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 240 data |= 3; 241 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 242 243 /* disable low power */ 244 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 245 data |= 1 << 3; 246 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 247 do { 248 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 249 } while (!(data & PERI_RST0_MMC0)); 250 251 /* unreset mmc0 clock domain */ 252 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 253 do { 254 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 255 } while (data & PERI_RST0_MMC0); 256 } 257 258 static void hikey_boardid_init(void) 259 { 260 u_register_t midr; 261 262 midr = read_midr(); 263 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 264 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 265 (unsigned int)midr); 266 267 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 268 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 269 270 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 271 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 272 } 273 274 static void hikey_sd_init(void) 275 { 276 /* switch pinmux to SD */ 277 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 278 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 279 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 280 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 281 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 282 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 283 284 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 285 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 286 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 287 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 288 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 289 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 290 291 /* set SD Card detect as nopull */ 292 mmio_write_32(IOCG_GPIO8, 0); 293 } 294 295 static void hikey_jumper_init(void) 296 { 297 /* set jumper detect as nopull */ 298 mmio_write_32(IOCG_GPIO24, 0); 299 /* set jumper detect as GPIO */ 300 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 301 } 302 303 void bl2_early_platform_setup(meminfo_t *mem_layout) 304 { 305 dw_mmc_params_t params; 306 307 /* Initialize the console to provide early debug support */ 308 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 309 310 /* Setup the BL2 memory layout */ 311 bl2_tzram_layout = *mem_layout; 312 313 /* Clear SRAM since it'll be used by MCU right now. */ 314 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 315 316 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 317 dsb(); 318 hikey_ddr_init(); 319 320 hikey_boardid_init(); 321 init_acpu_dvfs(); 322 hikey_sd_init(); 323 hikey_jumper_init(); 324 325 reset_dwmmc_clk(); 326 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 327 params.reg_base = DWMMC0_BASE; 328 params.desc_base = HIKEY_MMC_DESC_BASE; 329 params.desc_size = 1 << 20; 330 params.clk_rate = 24 * 1000 * 1000; 331 params.bus_width = EMMC_BUS_WIDTH_8; 332 params.flags = EMMC_FLAG_CMD23; 333 dw_mmc_init(¶ms); 334 335 hikey_io_setup(); 336 } 337 338 void bl2_plat_arch_setup(void) 339 { 340 hikey_init_mmu_el1(bl2_tzram_layout.total_base, 341 bl2_tzram_layout.total_size, 342 BL2_RO_BASE, 343 BL2_RO_LIMIT, 344 BL2_COHERENT_RAM_BASE, 345 BL2_COHERENT_RAM_LIMIT); 346 } 347 348 void bl2_platform_setup(void) 349 { 350 } 351