1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <emmc.h> 14 #include <errno.h> 15 #include <hi6220.h> 16 #include <hisi_mcu.h> 17 #include <hisi_sram_map.h> 18 #include <mmio.h> 19 #include <platform_def.h> 20 #include <sp804_delay_timer.h> 21 #include <string.h> 22 23 #include "hikey_def.h" 24 #include "hikey_private.h" 25 26 /* 27 * The next 2 constants identify the extents of the code & RO data region. 28 * These addresses are used by the MMU setup code and therefore they must be 29 * page-aligned. It is the responsibility of the linker script to ensure that 30 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 31 */ 32 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 33 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 34 35 /* 36 * The next 2 constants identify the extents of the coherent memory region. 37 * These addresses are used by the MMU setup code and therefore they must be 38 * page-aligned. It is the responsibility of the linker script to ensure that 39 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 40 * page-aligned addresses. 41 */ 42 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 43 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 44 45 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 46 47 typedef struct bl2_to_bl31_params_mem { 48 bl31_params_t bl31_params; 49 image_info_t bl31_image_info; 50 image_info_t bl32_image_info; 51 image_info_t bl33_image_info; 52 entry_point_info_t bl33_ep_info; 53 entry_point_info_t bl32_ep_info; 54 entry_point_info_t bl31_ep_info; 55 } bl2_to_bl31_params_mem_t; 56 57 static bl2_to_bl31_params_mem_t bl31_params_mem; 58 59 meminfo_t *bl2_plat_sec_mem_layout(void) 60 { 61 return &bl2_tzram_layout; 62 } 63 64 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 65 { 66 scp_bl2_meminfo->total_base = SCP_BL2_BASE; 67 scp_bl2_meminfo->total_size = SCP_BL2_SIZE; 68 scp_bl2_meminfo->free_base = SCP_BL2_BASE; 69 scp_bl2_meminfo->free_size = SCP_BL2_SIZE; 70 } 71 72 int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) 73 { 74 /* Enable MCU SRAM */ 75 hisi_mcu_enable_sram(); 76 77 /* Load MCU binary into SRAM */ 78 hisi_mcu_load_image(scp_bl2_image_info->image_base, 79 scp_bl2_image_info->image_size); 80 /* Let MCU running */ 81 hisi_mcu_start_run(); 82 83 INFO("%s: MCU PC is at 0x%x\n", 84 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 85 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 86 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 87 return 0; 88 } 89 90 bl31_params_t *bl2_plat_get_bl31_params(void) 91 { 92 bl31_params_t *bl2_to_bl31_params = NULL; 93 94 /* 95 * Initialise the memory for all the arguments that needs to 96 * be passed to BL3-1 97 */ 98 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 99 100 /* Assign memory for TF related information */ 101 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 102 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 103 104 /* Fill BL3-1 related information */ 105 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 106 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 107 VERSION_1, 0); 108 109 /* Fill BL3-2 related information if it exists */ 110 #if BL32_BASE 111 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 112 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 113 VERSION_1, 0); 114 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 115 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 116 VERSION_1, 0); 117 #endif 118 119 /* Fill BL3-3 related information */ 120 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 121 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 122 PARAM_EP, VERSION_1, 0); 123 124 /* BL3-3 expects to receive the primary CPU MPID (through x0) */ 125 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 126 127 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 128 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 129 VERSION_1, 0); 130 131 return bl2_to_bl31_params; 132 } 133 134 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 135 { 136 return &bl31_params_mem.bl31_ep_info; 137 } 138 139 void bl2_plat_set_bl31_ep_info(image_info_t *image, 140 entry_point_info_t *bl31_ep_info) 141 { 142 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 143 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 144 DISABLE_ALL_EXCEPTIONS); 145 } 146 147 void bl2_plat_set_bl33_ep_info(image_info_t *image, 148 entry_point_info_t *bl33_ep_info) 149 { 150 unsigned long el_status; 151 unsigned int mode; 152 153 /* Figure out what mode we enter the non-secure world in */ 154 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 155 el_status &= ID_AA64PFR0_ELX_MASK; 156 157 if (el_status) 158 mode = MODE_EL2; 159 else 160 mode = MODE_EL1; 161 162 /* 163 * TODO: Consider the possibility of specifying the SPSR in 164 * the FIP ToC and allowing the platform to have a say as 165 * well. 166 */ 167 bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, 168 DISABLE_ALL_EXCEPTIONS); 169 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 170 } 171 172 void bl2_plat_flush_bl31_params(void) 173 { 174 flush_dcache_range((unsigned long)&bl31_params_mem, 175 sizeof(bl2_to_bl31_params_mem_t)); 176 } 177 178 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 179 { 180 bl33_meminfo->total_base = DDR_BASE; 181 bl33_meminfo->total_size = DDR_SIZE; 182 bl33_meminfo->free_base = DDR_BASE; 183 bl33_meminfo->free_size = DDR_SIZE; 184 } 185 186 static void reset_dwmmc_clk(void) 187 { 188 unsigned int data; 189 190 /* disable mmc0 bus clock */ 191 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 192 do { 193 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 194 } while (data & PERI_CLK0_MMC0); 195 /* enable mmc0 bus clock */ 196 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 197 do { 198 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 199 } while (!(data & PERI_CLK0_MMC0)); 200 /* reset mmc0 clock domain */ 201 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 202 203 /* bypass mmc0 clock phase */ 204 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 205 data |= 3; 206 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 207 208 /* disable low power */ 209 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 210 data |= 1 << 3; 211 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 212 do { 213 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 214 } while (!(data & PERI_RST0_MMC0)); 215 216 /* unreset mmc0 clock domain */ 217 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 218 do { 219 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 220 } while (data & PERI_RST0_MMC0); 221 } 222 223 static void hikey_boardid_init(void) 224 { 225 u_register_t midr; 226 227 midr = read_midr(); 228 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 229 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 230 (unsigned int)midr); 231 232 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 233 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 234 235 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 236 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 237 } 238 239 static void hikey_sd_init(void) 240 { 241 /* switch pinmux to SD */ 242 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 243 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 244 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 245 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 246 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 247 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 248 249 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 250 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 251 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 252 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 253 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 254 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 255 256 /* set SD Card detect as nopull */ 257 mmio_write_32(IOCG_GPIO8, 0); 258 } 259 260 static void hikey_jumper_init(void) 261 { 262 /* set jumper detect as nopull */ 263 mmio_write_32(IOCG_GPIO24, 0); 264 /* set jumper detect as GPIO */ 265 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 266 } 267 268 void bl2_early_platform_setup(meminfo_t *mem_layout) 269 { 270 dw_mmc_params_t params; 271 272 /* Initialize the console to provide early debug support */ 273 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 274 275 /* Setup the BL2 memory layout */ 276 bl2_tzram_layout = *mem_layout; 277 278 /* Clear SRAM since it'll be used by MCU right now. */ 279 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 280 281 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 282 dsb(); 283 hikey_ddr_init(); 284 285 hikey_boardid_init(); 286 init_acpu_dvfs(); 287 hikey_sd_init(); 288 hikey_jumper_init(); 289 290 reset_dwmmc_clk(); 291 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 292 params.reg_base = DWMMC0_BASE; 293 params.desc_base = HIKEY_MMC_DESC_BASE; 294 params.desc_size = 1 << 20; 295 params.clk_rate = 24 * 1000 * 1000; 296 params.bus_width = EMMC_BUS_WIDTH_8; 297 params.flags = EMMC_FLAG_CMD23; 298 dw_mmc_init(¶ms); 299 300 hikey_io_setup(); 301 } 302 303 void bl2_plat_arch_setup(void) 304 { 305 hikey_init_mmu_el1(bl2_tzram_layout.total_base, 306 bl2_tzram_layout.total_size, 307 BL2_RO_BASE, 308 BL2_RO_LIMIT, 309 BL2_COHERENT_RAM_BASE, 310 BL2_COHERENT_RAM_LIMIT); 311 } 312 313 void bl2_platform_setup(void) 314 { 315 } 316