1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <emmc.h> 14 #include <errno.h> 15 #include <hi6220.h> 16 #include <hikey_def.h> 17 #include <hikey_layout.h> 18 #include <mmio.h> 19 #include <platform.h> 20 #include <string.h> 21 #include <tbbr/tbbr_img_desc.h> 22 23 #include "../../bl1/bl1_private.h" 24 #include "hikey_private.h" 25 26 /* Data structure which holds the extents of the trusted RAM for BL1 */ 27 static meminfo_t bl1_tzram_layout; 28 29 enum { 30 BOOT_NORMAL = 0, 31 BOOT_USB_DOWNLOAD, 32 BOOT_UART_DOWNLOAD, 33 }; 34 35 meminfo_t *bl1_plat_sec_mem_layout(void) 36 { 37 return &bl1_tzram_layout; 38 } 39 40 /******************************************************************************* 41 * Function that takes a memory layout into which BL2 has been loaded and 42 * populates a new memory layout for BL2 that ensures that BL1's data sections 43 * resident in secure RAM are not visible to BL2. 44 ******************************************************************************/ 45 void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 46 meminfo_t *bl2_mem_layout) 47 { 48 49 assert(bl1_mem_layout != NULL); 50 assert(bl2_mem_layout != NULL); 51 52 /* 53 * Cannot remove BL1 RW data from the scope of memory visible to BL2 54 * like arm platforms because they overlap in hikey 55 */ 56 bl2_mem_layout->total_base = BL2_BASE; 57 bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE; 58 59 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 60 } 61 62 /* 63 * Perform any BL1 specific platform actions. 64 */ 65 void bl1_early_platform_setup(void) 66 { 67 /* Initialize the console to provide early debug support */ 68 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 69 70 /* Allow BL1 to see the whole Trusted RAM */ 71 bl1_tzram_layout.total_base = BL1_RW_BASE; 72 bl1_tzram_layout.total_size = BL1_RW_SIZE; 73 74 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 75 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 76 } 77 78 /* 79 * Perform the very early platform specific architecture setup here. At the 80 * moment this only does basic initialization. Later architectural setup 81 * (bl1_arch_setup()) does not do anything platform specific. 82 */ 83 void bl1_plat_arch_setup(void) 84 { 85 hikey_init_mmu_el3(bl1_tzram_layout.total_base, 86 bl1_tzram_layout.total_size, 87 BL1_RO_BASE, 88 BL1_RO_LIMIT, 89 BL_COHERENT_RAM_BASE, 90 BL_COHERENT_RAM_END); 91 } 92 93 /* 94 * Function which will perform any remaining platform-specific setup that can 95 * occur after the MMU and data cache have been enabled. 96 */ 97 void bl1_platform_setup(void) 98 { 99 dw_mmc_params_t params; 100 101 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && 102 ((SRAM_BASE + SRAM_SIZE) >= 103 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE))); 104 hikey_sp804_init(); 105 hikey_gpio_init(); 106 hikey_pmussi_init(); 107 hikey_hi6553_init(); 108 109 hikey_rtc_init(); 110 111 hikey_mmc_pll_init(); 112 113 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 114 params.reg_base = DWMMC0_BASE; 115 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; 116 params.desc_size = 1 << 20; 117 params.clk_rate = 24 * 1000 * 1000; 118 params.bus_width = EMMC_BUS_WIDTH_8; 119 params.flags = EMMC_FLAG_CMD23; 120 dw_mmc_init(¶ms); 121 122 hikey_io_setup(); 123 } 124 125 /* 126 * The following function checks if Firmware update is needed, 127 * by checking if TOC in FIP image is valid or not. 128 */ 129 unsigned int bl1_plat_get_next_image_id(void) 130 { 131 int32_t boot_mode; 132 unsigned int ret; 133 134 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 135 switch (boot_mode) { 136 case BOOT_USB_DOWNLOAD: 137 case BOOT_UART_DOWNLOAD: 138 ret = NS_BL1U_IMAGE_ID; 139 break; 140 default: 141 WARN("Invalid boot mode is found:%d\n", boot_mode); 142 panic(); 143 } 144 return ret; 145 } 146 147 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 148 { 149 unsigned int index = 0; 150 151 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 152 if (bl1_tbbr_image_descs[index].image_id == image_id) 153 return &bl1_tbbr_image_descs[index]; 154 155 index++; 156 } 157 158 return NULL; 159 } 160 161 void bl1_plat_set_ep_info(unsigned int image_id, 162 entry_point_info_t *ep_info) 163 { 164 uint64_t data = 0; 165 166 if (image_id == BL2_IMAGE_ID) 167 panic(); 168 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 169 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 170 do { 171 data |= 3 << 20; 172 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data)); 173 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 174 } while ((data & (3 << 20)) != (3 << 20)); 175 INFO("cpacr_el1:0x%llx\n", data); 176 177 ep_info->args.arg0 = 0xffff & read_mpidr(); 178 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 179 DISABLE_ALL_EXCEPTIONS); 180 } 181