1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <emmc.h> 14 #include <errno.h> 15 #include <gpio.h> 16 #include <hi6220.h> 17 #include <hi6553.h> 18 #include <mmio.h> 19 #include <pl061_gpio.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 #include <sp804_delay_timer.h> 23 #include <string.h> 24 #include <tbbr/tbbr_img_desc.h> 25 26 #include "../../bl1/bl1_private.h" 27 #include "hikey_def.h" 28 #include "hikey_private.h" 29 30 /* 31 * Declarations of linker defined symbols which will help us find the layout 32 * of trusted RAM 33 */ 34 extern unsigned long __COHERENT_RAM_START__; 35 extern unsigned long __COHERENT_RAM_END__; 36 37 /* 38 * The next 2 constants identify the extents of the coherent memory region. 39 * These addresses are used by the MMU setup code and therefore they must be 40 * page-aligned. It is the responsibility of the linker script to ensure that 41 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 42 * page-aligned addresses. 43 */ 44 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 45 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 46 47 /* Data structure which holds the extents of the trusted RAM for BL1 */ 48 static meminfo_t bl1_tzram_layout; 49 50 enum { 51 BOOT_NORMAL = 0, 52 BOOT_USB_DOWNLOAD, 53 BOOT_UART_DOWNLOAD, 54 }; 55 56 meminfo_t *bl1_plat_sec_mem_layout(void) 57 { 58 return &bl1_tzram_layout; 59 } 60 61 /* 62 * Perform any BL1 specific platform actions. 63 */ 64 void bl1_early_platform_setup(void) 65 { 66 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; 67 68 /* Initialize the console to provide early debug support */ 69 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 70 71 /* Allow BL1 to see the whole Trusted RAM */ 72 bl1_tzram_layout.total_base = BL1_RW_BASE; 73 bl1_tzram_layout.total_size = BL1_RW_SIZE; 74 75 /* Calculate how much RAM BL1 is using and how much remains free */ 76 bl1_tzram_layout.free_base = BL1_RW_BASE; 77 bl1_tzram_layout.free_size = BL1_RW_SIZE; 78 reserve_mem(&bl1_tzram_layout.free_base, 79 &bl1_tzram_layout.free_size, 80 BL1_RAM_BASE, 81 bl1_size); 82 83 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 84 bl1_size); 85 } 86 87 /* 88 * Perform the very early platform specific architecture setup here. At the 89 * moment this only does basic initialization. Later architectural setup 90 * (bl1_arch_setup()) does not do anything platform specific. 91 */ 92 void bl1_plat_arch_setup(void) 93 { 94 hikey_init_mmu_el3(bl1_tzram_layout.total_base, 95 bl1_tzram_layout.total_size, 96 BL1_RO_BASE, 97 BL1_RO_LIMIT, 98 BL1_COHERENT_RAM_BASE, 99 BL1_COHERENT_RAM_LIMIT); 100 } 101 102 static void hikey_sp804_init(void) 103 { 104 uint32_t data; 105 106 /* select the clock of dual timer0 */ 107 data = mmio_read_32(AO_SC_TIMER_EN0); 108 while (data & 3) { 109 data &= ~3; 110 data |= 3 << 16; 111 mmio_write_32(AO_SC_TIMER_EN0, data); 112 data = mmio_read_32(AO_SC_TIMER_EN0); 113 } 114 /* enable the pclk of dual timer0 */ 115 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); 116 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) { 117 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0); 118 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); 119 } 120 /* reset dual timer0 */ 121 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 122 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0); 123 do { 124 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 125 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)); 126 /* unreset dual timer0 */ 127 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0); 128 do { 129 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 130 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0)); 131 132 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 133 } 134 135 static void hikey_gpio_init(void) 136 { 137 pl061_gpio_init(); 138 pl061_gpio_register(GPIO0_BASE, 0); 139 pl061_gpio_register(GPIO1_BASE, 1); 140 pl061_gpio_register(GPIO2_BASE, 2); 141 pl061_gpio_register(GPIO3_BASE, 3); 142 pl061_gpio_register(GPIO4_BASE, 4); 143 pl061_gpio_register(GPIO5_BASE, 5); 144 pl061_gpio_register(GPIO6_BASE, 6); 145 pl061_gpio_register(GPIO7_BASE, 7); 146 pl061_gpio_register(GPIO8_BASE, 8); 147 pl061_gpio_register(GPIO9_BASE, 9); 148 pl061_gpio_register(GPIO10_BASE, 10); 149 pl061_gpio_register(GPIO11_BASE, 11); 150 pl061_gpio_register(GPIO12_BASE, 12); 151 pl061_gpio_register(GPIO13_BASE, 13); 152 pl061_gpio_register(GPIO14_BASE, 14); 153 pl061_gpio_register(GPIO15_BASE, 15); 154 pl061_gpio_register(GPIO16_BASE, 16); 155 pl061_gpio_register(GPIO17_BASE, 17); 156 pl061_gpio_register(GPIO18_BASE, 18); 157 pl061_gpio_register(GPIO19_BASE, 19); 158 159 /* Power on indicator LED (USER_LED1). */ 160 gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */ 161 gpio_set_value(32, GPIO_LEVEL_HIGH); 162 gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */ 163 gpio_set_value(33, GPIO_LEVEL_LOW); 164 gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */ 165 gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */ 166 } 167 168 static void hikey_pmussi_init(void) 169 { 170 uint32_t data; 171 172 /* Initialize PWR_HOLD GPIO */ 173 gpio_set_direction(0, GPIO_DIR_OUT); 174 gpio_set_value(0, GPIO_LEVEL_LOW); 175 176 /* 177 * After reset, PMUSSI stays in reset mode. 178 * Now make it out of reset. 179 */ 180 mmio_write_32(AO_SC_PERIPH_RSTDIS4, 181 AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 182 do { 183 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); 184 } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N); 185 186 /* Set PMUSSI clock latency for read operation. */ 187 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); 188 data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK; 189 data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3; 190 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data); 191 192 /* enable PMUSSI clock */ 193 data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU | 194 AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU; 195 mmio_write_32(AO_SC_PERIPH_CLKEN5, data); 196 data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI; 197 mmio_write_32(AO_SC_PERIPH_CLKEN4, data); 198 199 gpio_set_value(0, GPIO_LEVEL_HIGH); 200 } 201 202 static void hikey_hi6553_init(void) 203 { 204 uint8_t data; 205 206 mmio_write_8(HI6553_PERI_EN_MARK, 0x1e); 207 mmio_write_8(HI6553_NP_REG_ADJ1, 0); 208 data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC | 209 DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2; 210 mmio_write_8(HI6553_DISABLE6_XO_CLK, data); 211 212 /* configure BUCK0 & BUCK1 */ 213 mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e); 214 mmio_write_8(HI6553_BUCK0_CTRL7, 0x10); 215 mmio_write_8(HI6553_BUCK1_CTRL7, 0x10); 216 mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e); 217 mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e); 218 mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc); 219 mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc); 220 221 /* configure BUCK2 */ 222 mmio_write_8(HI6553_BUCK2_REG1, 0x4f); 223 mmio_write_8(HI6553_BUCK2_REG5, 0x99); 224 mmio_write_8(HI6553_BUCK2_REG6, 0x45); 225 mdelay(1); 226 mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22); 227 mdelay(1); 228 229 /* configure BUCK3 */ 230 mmio_write_8(HI6553_BUCK3_REG3, 0x02); 231 mmio_write_8(HI6553_BUCK3_REG5, 0x99); 232 mmio_write_8(HI6553_BUCK3_REG6, 0x41); 233 mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02); 234 mdelay(1); 235 236 /* configure BUCK4 */ 237 mmio_write_8(HI6553_BUCK4_REG2, 0x9a); 238 mmio_write_8(HI6553_BUCK4_REG5, 0x99); 239 mmio_write_8(HI6553_BUCK4_REG6, 0x45); 240 241 /* configure LDO20 */ 242 mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50); 243 244 mmio_write_8(HI6553_NP_REG_CHG, 0x0f); 245 mmio_write_8(HI6553_CLK_TOP0, 0x06); 246 mmio_write_8(HI6553_CLK_TOP3, 0xc0); 247 mmio_write_8(HI6553_CLK_TOP4, 0x00); 248 249 /* configure LDO7 & LDO10 for SD slot */ 250 /* enable LDO7 */ 251 data = mmio_read_8(HI6553_LDO7_REG_ADJ); 252 data = (data & 0xf8) | 0x2; 253 mmio_write_8(HI6553_LDO7_REG_ADJ, data); 254 mdelay(5); 255 mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6); 256 mdelay(5); 257 /* enable LDO10 */ 258 data = mmio_read_8(HI6553_LDO10_REG_ADJ); 259 data = (data & 0xf8) | 0x5; 260 mmio_write_8(HI6553_LDO10_REG_ADJ, data); 261 mdelay(5); 262 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1); 263 mdelay(5); 264 /* enable LDO15 */ 265 data = mmio_read_8(HI6553_LDO15_REG_ADJ); 266 data = (data & 0xf8) | 0x4; 267 mmio_write_8(HI6553_LDO15_REG_ADJ, data); 268 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6); 269 mdelay(5); 270 /* enable LDO19 */ 271 data = mmio_read_8(HI6553_LDO19_REG_ADJ); 272 data |= 0x7; 273 mmio_write_8(HI6553_LDO19_REG_ADJ, data); 274 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2); 275 mdelay(5); 276 /* enable LDO21 */ 277 data = mmio_read_8(HI6553_LDO21_REG_ADJ); 278 data = (data & 0xf8) | 0x3; 279 mmio_write_8(HI6553_LDO21_REG_ADJ, data); 280 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4); 281 mdelay(5); 282 /* enable LDO22 */ 283 data = mmio_read_8(HI6553_LDO22_REG_ADJ); 284 data = (data & 0xf8) | 0x7; 285 mmio_write_8(HI6553_LDO22_REG_ADJ, data); 286 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5); 287 mdelay(5); 288 289 /* select 32.764KHz */ 290 mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01); 291 292 /* Disable vbus_det interrupts */ 293 data = mmio_read_8(HI6553_IRQ2_MASK); 294 data = data | 0x3; 295 mmio_write_8(HI6553_IRQ2_MASK, data); 296 } 297 298 static void init_mmc0_pll(void) 299 { 300 unsigned int data; 301 302 /* select SYSPLL as the source of MMC0 */ 303 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ 304 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21); 305 do { 306 data = mmio_read_32(PERI_SC_CLK_SEL0); 307 } while (!(data & (1 << 5))); 308 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ 309 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29); 310 do { 311 data = mmio_read_32(PERI_SC_CLK_SEL0); 312 } while (data & (1 << 13)); 313 314 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0)); 315 do { 316 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 317 } while (!(data & (1 << 0))); 318 319 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 320 data |= 1 << 1; 321 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 322 323 do { 324 mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb); 325 data = mmio_read_32(PERI_SC_CLKCFG8BIT1); 326 } while ((data & 0xb) != 0xb); 327 } 328 329 static void reset_mmc0_clk(void) 330 { 331 unsigned int data; 332 333 /* disable mmc0 bus clock */ 334 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 335 do { 336 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 337 } while (data & PERI_CLK0_MMC0); 338 /* enable mmc0 bus clock */ 339 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 340 do { 341 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 342 } while (!(data & PERI_CLK0_MMC0)); 343 /* reset mmc0 clock domain */ 344 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 345 346 /* bypass mmc0 clock phase */ 347 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 348 data |= 3; 349 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 350 351 /* disable low power */ 352 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 353 data |= 1 << 3; 354 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 355 do { 356 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 357 } while (!(data & PERI_RST0_MMC0)); 358 359 /* unreset mmc0 clock domain */ 360 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 361 do { 362 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 363 } while (data & PERI_RST0_MMC0); 364 } 365 366 static void init_media_clk(void) 367 { 368 unsigned int data, value; 369 370 data = mmio_read_32(PMCTRL_MEDPLLCTRL); 371 data |= 1; 372 mmio_write_32(PMCTRL_MEDPLLCTRL, data); 373 374 for (;;) { 375 data = mmio_read_32(PMCTRL_MEDPLLCTRL); 376 value = 1 << 28; 377 if ((data & value) == value) 378 break; 379 } 380 381 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 382 data = 1 << 10; 383 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 384 } 385 386 static void init_mmc1_pll(void) 387 { 388 uint32_t data; 389 390 /* select SYSPLL as the source of MMC1 */ 391 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ 392 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27); 393 do { 394 data = mmio_read_32(PERI_SC_CLK_SEL0); 395 } while (!(data & (1 << 11))); 396 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ 397 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30); 398 do { 399 data = mmio_read_32(PERI_SC_CLK_SEL0); 400 } while (data & (1 << 14)); 401 402 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1)); 403 do { 404 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 405 } while (!(data & (1 << 1))); 406 407 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); 408 data |= 1 << 2; 409 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); 410 411 do { 412 /* 1.2GHz / 50 = 24MHz */ 413 mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7)); 414 data = mmio_read_32(PERI_SC_CLKCFG8BIT2); 415 } while ((data & 0x31) != 0x31); 416 } 417 418 static void reset_mmc1_clk(void) 419 { 420 unsigned int data; 421 422 /* disable mmc1 bus clock */ 423 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1); 424 do { 425 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 426 } while (data & PERI_CLK0_MMC1); 427 /* enable mmc1 bus clock */ 428 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1); 429 do { 430 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 431 } while (!(data & PERI_CLK0_MMC1)); 432 /* reset mmc1 clock domain */ 433 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1); 434 435 /* bypass mmc1 clock phase */ 436 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 437 data |= 3 << 2; 438 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 439 440 /* disable low power */ 441 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 442 data |= 1 << 4; 443 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 444 do { 445 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 446 } while (!(data & PERI_RST0_MMC1)); 447 448 /* unreset mmc0 clock domain */ 449 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1); 450 do { 451 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 452 } while (data & PERI_RST0_MMC1); 453 } 454 455 /* Initialize PLL of both eMMC and SD controllers. */ 456 static void hikey_mmc_pll_init(void) 457 { 458 init_mmc0_pll(); 459 reset_mmc0_clk(); 460 init_media_clk(); 461 462 dsb(); 463 464 init_mmc1_pll(); 465 reset_mmc1_clk(); 466 } 467 468 /* 469 * Function which will perform any remaining platform-specific setup that can 470 * occur after the MMU and data cache have been enabled. 471 */ 472 void bl1_platform_setup(void) 473 { 474 dw_mmc_params_t params; 475 476 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && 477 ((SRAM_BASE + SRAM_SIZE) >= 478 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE))); 479 hikey_sp804_init(); 480 hikey_gpio_init(); 481 hikey_pmussi_init(); 482 hikey_hi6553_init(); 483 484 hikey_mmc_pll_init(); 485 486 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 487 params.reg_base = DWMMC0_BASE; 488 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; 489 params.desc_size = 1 << 20; 490 params.clk_rate = 24 * 1000 * 1000; 491 params.bus_width = EMMC_BUS_WIDTH_8; 492 params.flags = EMMC_FLAG_CMD23; 493 dw_mmc_init(¶ms); 494 495 hikey_io_setup(); 496 } 497 498 /* 499 * The following function checks if Firmware update is needed, 500 * by checking if TOC in FIP image is valid or not. 501 */ 502 unsigned int bl1_plat_get_next_image_id(void) 503 { 504 int32_t boot_mode; 505 unsigned int ret; 506 507 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 508 switch (boot_mode) { 509 case BOOT_NORMAL: 510 ret = BL2_IMAGE_ID; 511 break; 512 case BOOT_USB_DOWNLOAD: 513 case BOOT_UART_DOWNLOAD: 514 ret = NS_BL1U_IMAGE_ID; 515 break; 516 default: 517 WARN("Invalid boot mode is found:%d\n", boot_mode); 518 panic(); 519 } 520 return ret; 521 } 522 523 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 524 { 525 unsigned int index = 0; 526 527 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 528 if (bl1_tbbr_image_descs[index].image_id == image_id) 529 return &bl1_tbbr_image_descs[index]; 530 531 index++; 532 } 533 534 return NULL; 535 } 536 537 void bl1_plat_set_ep_info(unsigned int image_id, 538 entry_point_info_t *ep_info) 539 { 540 unsigned int data = 0; 541 542 if (image_id == BL2_IMAGE_ID) 543 return; 544 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 545 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 546 do { 547 data |= 3 << 20; 548 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data)); 549 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 550 } while ((data & (3 << 20)) != (3 << 20)); 551 INFO("cpacr_el1:0x%x\n", data); 552 553 ep_info->args.arg0 = 0xffff & read_mpidr(); 554 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 555 DISABLE_ALL_EXCEPTIONS); 556 } 557