108b167e9SHaojian Zhuang /* 208b167e9SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 308b167e9SHaojian Zhuang * 408b167e9SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 508b167e9SHaojian Zhuang */ 608b167e9SHaojian Zhuang 708b167e9SHaojian Zhuang #include <arch_helpers.h> 808b167e9SHaojian Zhuang #include <arm_gic.h> 908b167e9SHaojian Zhuang #include <assert.h> 1008b167e9SHaojian Zhuang #include <bl_common.h> 1108b167e9SHaojian Zhuang #include <debug.h> 1208b167e9SHaojian Zhuang #include <mmio.h> 1308b167e9SHaojian Zhuang #include <platform.h> 1408b167e9SHaojian Zhuang #include <platform_def.h> 1508b167e9SHaojian Zhuang #include <xlat_tables.h> 1608b167e9SHaojian Zhuang 1708b167e9SHaojian Zhuang #include "../hikey_def.h" 1808b167e9SHaojian Zhuang 1908b167e9SHaojian Zhuang #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ 2008b167e9SHaojian Zhuang DDR_SIZE, \ 2108b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_NS) 2208b167e9SHaojian Zhuang 2308b167e9SHaojian Zhuang #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \ 2408b167e9SHaojian Zhuang DEVICE_SIZE, \ 2508b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 2608b167e9SHaojian Zhuang 27*3b6e88a2SVictor Chong #define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ 28*3b6e88a2SVictor Chong TSP_SEC_MEM_SIZE, \ 29*3b6e88a2SVictor Chong MT_MEMORY | MT_RW | MT_SECURE) 30*3b6e88a2SVictor Chong 3108b167e9SHaojian Zhuang #define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \ 3208b167e9SHaojian Zhuang BL1_XG2RAM0_OFFSET, \ 3308b167e9SHaojian Zhuang MT_DEVICE | MT_RO | MT_SECURE) 3408b167e9SHaojian Zhuang 3508b167e9SHaojian Zhuang #define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \ 3608b167e9SHaojian Zhuang SRAM_SIZE, \ 3708b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 3808b167e9SHaojian Zhuang 3908b167e9SHaojian Zhuang /* 4008b167e9SHaojian Zhuang * BL1 needs to access the areas of MMC_SRAM. 4108b167e9SHaojian Zhuang * BL1 loads BL2 from eMMC into SRAM before DDR initialized. 4208b167e9SHaojian Zhuang */ 4308b167e9SHaojian Zhuang #define MAP_MMC_SRAM MAP_REGION_FLAT(HIKEY_BL1_MMC_DESC_BASE, \ 4408b167e9SHaojian Zhuang HIKEY_BL1_MMC_DESC_SIZE + \ 4508b167e9SHaojian Zhuang HIKEY_BL1_MMC_DATA_SIZE, \ 4608b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 4708b167e9SHaojian Zhuang 4808b167e9SHaojian Zhuang /* 4908b167e9SHaojian Zhuang * Table of regions for different BL stages to map using the MMU. 5008b167e9SHaojian Zhuang * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 5108b167e9SHaojian Zhuang * hikey_init_mmu_elx() will give the available subset of that, 5208b167e9SHaojian Zhuang */ 5308b167e9SHaojian Zhuang #if IMAGE_BL1 5408b167e9SHaojian Zhuang static const mmap_region_t hikey_mmap[] = { 5508b167e9SHaojian Zhuang MAP_DEVICE, 5608b167e9SHaojian Zhuang MAP_ROM_PARAM, 5708b167e9SHaojian Zhuang MAP_MMC_SRAM, 5808b167e9SHaojian Zhuang {0} 5908b167e9SHaojian Zhuang }; 6008b167e9SHaojian Zhuang #endif 6108b167e9SHaojian Zhuang 6208b167e9SHaojian Zhuang #if IMAGE_BL2 6308b167e9SHaojian Zhuang static const mmap_region_t hikey_mmap[] = { 6408b167e9SHaojian Zhuang MAP_DDR, 6508b167e9SHaojian Zhuang MAP_DEVICE, 66*3b6e88a2SVictor Chong MAP_TSP_MEM, 6708b167e9SHaojian Zhuang {0} 6808b167e9SHaojian Zhuang }; 6908b167e9SHaojian Zhuang #endif 7008b167e9SHaojian Zhuang 7108b167e9SHaojian Zhuang #if IMAGE_BL31 7208b167e9SHaojian Zhuang static const mmap_region_t hikey_mmap[] = { 7308b167e9SHaojian Zhuang MAP_DEVICE, 7408b167e9SHaojian Zhuang MAP_SRAM, 75*3b6e88a2SVictor Chong MAP_TSP_MEM, 76*3b6e88a2SVictor Chong {0} 77*3b6e88a2SVictor Chong }; 78*3b6e88a2SVictor Chong #endif 79*3b6e88a2SVictor Chong 80*3b6e88a2SVictor Chong #if IMAGE_BL32 81*3b6e88a2SVictor Chong static const mmap_region_t hikey_mmap[] = { 82*3b6e88a2SVictor Chong MAP_DEVICE, 83*3b6e88a2SVictor Chong MAP_DDR, 8408b167e9SHaojian Zhuang {0} 8508b167e9SHaojian Zhuang }; 8608b167e9SHaojian Zhuang #endif 8708b167e9SHaojian Zhuang 8808b167e9SHaojian Zhuang /* 8908b167e9SHaojian Zhuang * Macro generating the code for the function setting up the pagetables as per 9008b167e9SHaojian Zhuang * the platform memory map & initialize the mmu, for the given exception level 9108b167e9SHaojian Zhuang */ 9208b167e9SHaojian Zhuang #define HIKEY_CONFIGURE_MMU_EL(_el) \ 9308b167e9SHaojian Zhuang void hikey_init_mmu_el##_el(unsigned long total_base, \ 9408b167e9SHaojian Zhuang unsigned long total_size, \ 9508b167e9SHaojian Zhuang unsigned long ro_start, \ 9608b167e9SHaojian Zhuang unsigned long ro_limit, \ 9708b167e9SHaojian Zhuang unsigned long coh_start, \ 9808b167e9SHaojian Zhuang unsigned long coh_limit) \ 9908b167e9SHaojian Zhuang { \ 10008b167e9SHaojian Zhuang mmap_add_region(total_base, total_base, \ 10108b167e9SHaojian Zhuang total_size, \ 10208b167e9SHaojian Zhuang MT_MEMORY | MT_RW | MT_SECURE); \ 10308b167e9SHaojian Zhuang mmap_add_region(ro_start, ro_start, \ 10408b167e9SHaojian Zhuang ro_limit - ro_start, \ 10508b167e9SHaojian Zhuang MT_MEMORY | MT_RO | MT_SECURE); \ 10608b167e9SHaojian Zhuang mmap_add_region(coh_start, coh_start, \ 10708b167e9SHaojian Zhuang coh_limit - coh_start, \ 10808b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE); \ 10908b167e9SHaojian Zhuang mmap_add(hikey_mmap); \ 11008b167e9SHaojian Zhuang init_xlat_tables(); \ 11108b167e9SHaojian Zhuang \ 11208b167e9SHaojian Zhuang enable_mmu_el##_el(0); \ 11308b167e9SHaojian Zhuang } 11408b167e9SHaojian Zhuang 11508b167e9SHaojian Zhuang /* Define EL1 and EL3 variants of the function initialising the MMU */ 11608b167e9SHaojian Zhuang HIKEY_CONFIGURE_MMU_EL(1) 11708b167e9SHaojian Zhuang HIKEY_CONFIGURE_MMU_EL(3) 11808b167e9SHaojian Zhuang 11908b167e9SHaojian Zhuang unsigned long plat_get_ns_image_entrypoint(void) 12008b167e9SHaojian Zhuang { 12108b167e9SHaojian Zhuang return HIKEY_NS_IMAGE_OFFSET; 12208b167e9SHaojian Zhuang } 12308b167e9SHaojian Zhuang 12408b167e9SHaojian Zhuang unsigned int plat_get_syscnt_freq2(void) 12508b167e9SHaojian Zhuang { 12608b167e9SHaojian Zhuang return 1200000; 12708b167e9SHaojian Zhuang } 128