1*08b167e9SHaojian Zhuang /* 2*08b167e9SHaojian Zhuang * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*08b167e9SHaojian Zhuang * 4*08b167e9SHaojian Zhuang * SPDX-License-Identifier: BSD-3-Clause 5*08b167e9SHaojian Zhuang */ 6*08b167e9SHaojian Zhuang 7*08b167e9SHaojian Zhuang #include <arch_helpers.h> 8*08b167e9SHaojian Zhuang #include <arm_gic.h> 9*08b167e9SHaojian Zhuang #include <assert.h> 10*08b167e9SHaojian Zhuang #include <bl_common.h> 11*08b167e9SHaojian Zhuang #include <debug.h> 12*08b167e9SHaojian Zhuang #include <mmio.h> 13*08b167e9SHaojian Zhuang #include <platform.h> 14*08b167e9SHaojian Zhuang #include <platform_def.h> 15*08b167e9SHaojian Zhuang #include <xlat_tables.h> 16*08b167e9SHaojian Zhuang 17*08b167e9SHaojian Zhuang #include "../hikey_def.h" 18*08b167e9SHaojian Zhuang 19*08b167e9SHaojian Zhuang #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ 20*08b167e9SHaojian Zhuang DDR_SIZE, \ 21*08b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_NS) 22*08b167e9SHaojian Zhuang 23*08b167e9SHaojian Zhuang #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \ 24*08b167e9SHaojian Zhuang DEVICE_SIZE, \ 25*08b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 26*08b167e9SHaojian Zhuang 27*08b167e9SHaojian Zhuang #define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \ 28*08b167e9SHaojian Zhuang BL1_XG2RAM0_OFFSET, \ 29*08b167e9SHaojian Zhuang MT_DEVICE | MT_RO | MT_SECURE) 30*08b167e9SHaojian Zhuang 31*08b167e9SHaojian Zhuang #define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \ 32*08b167e9SHaojian Zhuang SRAM_SIZE, \ 33*08b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 34*08b167e9SHaojian Zhuang 35*08b167e9SHaojian Zhuang /* 36*08b167e9SHaojian Zhuang * BL1 needs to access the areas of MMC_SRAM. 37*08b167e9SHaojian Zhuang * BL1 loads BL2 from eMMC into SRAM before DDR initialized. 38*08b167e9SHaojian Zhuang */ 39*08b167e9SHaojian Zhuang #define MAP_MMC_SRAM MAP_REGION_FLAT(HIKEY_BL1_MMC_DESC_BASE, \ 40*08b167e9SHaojian Zhuang HIKEY_BL1_MMC_DESC_SIZE + \ 41*08b167e9SHaojian Zhuang HIKEY_BL1_MMC_DATA_SIZE, \ 42*08b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE) 43*08b167e9SHaojian Zhuang 44*08b167e9SHaojian Zhuang /* 45*08b167e9SHaojian Zhuang * Table of regions for different BL stages to map using the MMU. 46*08b167e9SHaojian Zhuang * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 47*08b167e9SHaojian Zhuang * hikey_init_mmu_elx() will give the available subset of that, 48*08b167e9SHaojian Zhuang */ 49*08b167e9SHaojian Zhuang #if IMAGE_BL1 50*08b167e9SHaojian Zhuang static const mmap_region_t hikey_mmap[] = { 51*08b167e9SHaojian Zhuang MAP_DEVICE, 52*08b167e9SHaojian Zhuang MAP_ROM_PARAM, 53*08b167e9SHaojian Zhuang MAP_MMC_SRAM, 54*08b167e9SHaojian Zhuang {0} 55*08b167e9SHaojian Zhuang }; 56*08b167e9SHaojian Zhuang #endif 57*08b167e9SHaojian Zhuang 58*08b167e9SHaojian Zhuang #if IMAGE_BL2 59*08b167e9SHaojian Zhuang static const mmap_region_t hikey_mmap[] = { 60*08b167e9SHaojian Zhuang MAP_DDR, 61*08b167e9SHaojian Zhuang MAP_DEVICE, 62*08b167e9SHaojian Zhuang {0} 63*08b167e9SHaojian Zhuang }; 64*08b167e9SHaojian Zhuang #endif 65*08b167e9SHaojian Zhuang 66*08b167e9SHaojian Zhuang #if IMAGE_BL31 67*08b167e9SHaojian Zhuang static const mmap_region_t hikey_mmap[] = { 68*08b167e9SHaojian Zhuang MAP_DEVICE, 69*08b167e9SHaojian Zhuang MAP_SRAM, 70*08b167e9SHaojian Zhuang {0} 71*08b167e9SHaojian Zhuang }; 72*08b167e9SHaojian Zhuang #endif 73*08b167e9SHaojian Zhuang 74*08b167e9SHaojian Zhuang /* 75*08b167e9SHaojian Zhuang * Macro generating the code for the function setting up the pagetables as per 76*08b167e9SHaojian Zhuang * the platform memory map & initialize the mmu, for the given exception level 77*08b167e9SHaojian Zhuang */ 78*08b167e9SHaojian Zhuang #define HIKEY_CONFIGURE_MMU_EL(_el) \ 79*08b167e9SHaojian Zhuang void hikey_init_mmu_el##_el(unsigned long total_base, \ 80*08b167e9SHaojian Zhuang unsigned long total_size, \ 81*08b167e9SHaojian Zhuang unsigned long ro_start, \ 82*08b167e9SHaojian Zhuang unsigned long ro_limit, \ 83*08b167e9SHaojian Zhuang unsigned long coh_start, \ 84*08b167e9SHaojian Zhuang unsigned long coh_limit) \ 85*08b167e9SHaojian Zhuang { \ 86*08b167e9SHaojian Zhuang mmap_add_region(total_base, total_base, \ 87*08b167e9SHaojian Zhuang total_size, \ 88*08b167e9SHaojian Zhuang MT_MEMORY | MT_RW | MT_SECURE); \ 89*08b167e9SHaojian Zhuang mmap_add_region(ro_start, ro_start, \ 90*08b167e9SHaojian Zhuang ro_limit - ro_start, \ 91*08b167e9SHaojian Zhuang MT_MEMORY | MT_RO | MT_SECURE); \ 92*08b167e9SHaojian Zhuang mmap_add_region(coh_start, coh_start, \ 93*08b167e9SHaojian Zhuang coh_limit - coh_start, \ 94*08b167e9SHaojian Zhuang MT_DEVICE | MT_RW | MT_SECURE); \ 95*08b167e9SHaojian Zhuang mmap_add(hikey_mmap); \ 96*08b167e9SHaojian Zhuang init_xlat_tables(); \ 97*08b167e9SHaojian Zhuang \ 98*08b167e9SHaojian Zhuang enable_mmu_el##_el(0); \ 99*08b167e9SHaojian Zhuang } 100*08b167e9SHaojian Zhuang 101*08b167e9SHaojian Zhuang /* Define EL1 and EL3 variants of the function initialising the MMU */ 102*08b167e9SHaojian Zhuang HIKEY_CONFIGURE_MMU_EL(1) 103*08b167e9SHaojian Zhuang HIKEY_CONFIGURE_MMU_EL(3) 104*08b167e9SHaojian Zhuang 105*08b167e9SHaojian Zhuang unsigned long plat_get_ns_image_entrypoint(void) 106*08b167e9SHaojian Zhuang { 107*08b167e9SHaojian Zhuang return HIKEY_NS_IMAGE_OFFSET; 108*08b167e9SHaojian Zhuang } 109*08b167e9SHaojian Zhuang 110*08b167e9SHaojian Zhuang unsigned int plat_get_syscnt_freq2(void) 111*08b167e9SHaojian Zhuang { 112*08b167e9SHaojian Zhuang return 1200000; 113*08b167e9SHaojian Zhuang } 114