1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <bl31/interrupt_mgmt.h> 15 #include <drivers/arm/gic_common.h> 16 #include <drivers/arm/gicv3.h> 17 #include <lib/cassert.h> 18 #include <plat/common/platform.h> 19 20 #ifdef IMAGE_BL31 21 22 /* 23 * The following platform GIC functions are weakly defined. They 24 * provide typical implementations that may be re-used by multiple 25 * platforms but may also be overridden by a platform if required. 26 */ 27 #pragma weak plat_ic_get_pending_interrupt_id 28 #pragma weak plat_ic_get_pending_interrupt_type 29 #pragma weak plat_ic_acknowledge_interrupt 30 #pragma weak plat_ic_get_interrupt_type 31 #pragma weak plat_ic_end_of_interrupt 32 #pragma weak plat_interrupt_type_to_line 33 34 #pragma weak plat_ic_get_running_priority 35 #pragma weak plat_ic_is_spi 36 #pragma weak plat_ic_is_ppi 37 #pragma weak plat_ic_is_sgi 38 #pragma weak plat_ic_get_interrupt_active 39 #pragma weak plat_ic_enable_interrupt 40 #pragma weak plat_ic_disable_interrupt 41 #pragma weak plat_ic_set_interrupt_priority 42 #pragma weak plat_ic_set_interrupt_type 43 #pragma weak plat_ic_raise_el3_sgi 44 #pragma weak plat_ic_raise_ns_sgi 45 #pragma weak plat_ic_raise_s_el1_sgi 46 #pragma weak plat_ic_set_spi_routing 47 #pragma weak plat_ic_set_interrupt_pending 48 #pragma weak plat_ic_clear_interrupt_pending 49 50 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 51 (INTR_TYPE_NS == INTR_GROUP1NS) && 52 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 53 54 /* 55 * This function returns the highest priority pending interrupt at 56 * the Interrupt controller 57 */ 58 uint32_t plat_ic_get_pending_interrupt_id(void) 59 { 60 unsigned int irqnr; 61 62 assert(IS_IN_EL3()); 63 irqnr = gicv3_get_pending_interrupt_id(); 64 return gicv3_is_intr_id_special_identifier(irqnr) ? 65 INTR_ID_UNAVAILABLE : irqnr; 66 } 67 68 /* 69 * This function returns the type of the highest priority pending interrupt 70 * at the Interrupt controller. In the case of GICv3, the Highest Priority 71 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 72 * the id of the pending interrupt. The type of interrupt depends upon the 73 * id value as follows. 74 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 75 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 76 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 77 * type. 78 * 4. All other interrupt id's are reported as EL3 interrupt. 79 */ 80 uint32_t plat_ic_get_pending_interrupt_type(void) 81 { 82 unsigned int irqnr; 83 uint32_t type; 84 85 assert(IS_IN_EL3()); 86 irqnr = gicv3_get_pending_interrupt_type(); 87 88 switch (irqnr) { 89 case PENDING_G1S_INTID: 90 type = INTR_TYPE_S_EL1; 91 break; 92 case PENDING_G1NS_INTID: 93 type = INTR_TYPE_NS; 94 break; 95 case GIC_SPURIOUS_INTERRUPT: 96 type = INTR_TYPE_INVAL; 97 break; 98 default: 99 type = INTR_TYPE_EL3; 100 break; 101 } 102 103 return type; 104 } 105 106 /* 107 * This function returns the highest priority pending interrupt at 108 * the Interrupt controller and indicates to the Interrupt controller 109 * that the interrupt processing has started. 110 */ 111 uint32_t plat_ic_acknowledge_interrupt(void) 112 { 113 assert(IS_IN_EL3()); 114 return gicv3_acknowledge_interrupt(); 115 } 116 117 /* 118 * This function returns the type of the interrupt `id`, depending on how 119 * the interrupt has been configured in the interrupt controller 120 */ 121 uint32_t plat_ic_get_interrupt_type(uint32_t id) 122 { 123 assert(IS_IN_EL3()); 124 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 125 } 126 127 /* 128 * This functions is used to indicate to the interrupt controller that 129 * the processing of the interrupt corresponding to the `id` has 130 * finished. 131 */ 132 void plat_ic_end_of_interrupt(uint32_t id) 133 { 134 assert(IS_IN_EL3()); 135 gicv3_end_of_interrupt(id); 136 } 137 138 /* 139 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 140 * The interrupt controller knows which pin/line it uses to signal a type of 141 * interrupt. It lets the interrupt management framework determine for a type of 142 * interrupt and security state, which line should be used in the SCR_EL3 to 143 * control its routing to EL3. The interrupt line is represented as the bit 144 * position of the IRQ or FIQ bit in the SCR_EL3. 145 */ 146 uint32_t plat_interrupt_type_to_line(uint32_t type, 147 uint32_t security_state) 148 { 149 assert((type == INTR_TYPE_S_EL1) || 150 (type == INTR_TYPE_EL3) || 151 (type == INTR_TYPE_NS)); 152 153 assert(sec_state_is_valid(security_state)); 154 assert(IS_IN_EL3()); 155 156 switch (type) { 157 case INTR_TYPE_S_EL1: 158 /* 159 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 160 * and as FIQ in the NS-EL0/1/2 contexts 161 */ 162 if (security_state == SECURE) 163 return __builtin_ctz(SCR_IRQ_BIT); 164 else 165 return __builtin_ctz(SCR_FIQ_BIT); 166 assert(0); /* Unreachable */ 167 case INTR_TYPE_NS: 168 /* 169 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 170 * contexts and as IRQ in the NS-EL0/1/2 contexts. 171 */ 172 if (security_state == SECURE) 173 return __builtin_ctz(SCR_FIQ_BIT); 174 else 175 return __builtin_ctz(SCR_IRQ_BIT); 176 assert(0); /* Unreachable */ 177 case INTR_TYPE_EL3: 178 /* 179 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 180 * NS-EL0/1/2 contexts 181 */ 182 return __builtin_ctz(SCR_FIQ_BIT); 183 default: 184 panic(); 185 } 186 } 187 188 unsigned int plat_ic_get_running_priority(void) 189 { 190 return gicv3_get_running_priority(); 191 } 192 193 int plat_ic_is_spi(unsigned int id) 194 { 195 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 196 } 197 198 int plat_ic_is_ppi(unsigned int id) 199 { 200 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 201 } 202 203 int plat_ic_is_sgi(unsigned int id) 204 { 205 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 206 } 207 208 unsigned int plat_ic_get_interrupt_active(unsigned int id) 209 { 210 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 211 } 212 213 void plat_ic_enable_interrupt(unsigned int id) 214 { 215 gicv3_enable_interrupt(id, plat_my_core_pos()); 216 } 217 218 void plat_ic_disable_interrupt(unsigned int id) 219 { 220 gicv3_disable_interrupt(id, plat_my_core_pos()); 221 } 222 223 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 224 { 225 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); 226 } 227 228 int plat_ic_has_interrupt_type(unsigned int type) 229 { 230 assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || 231 (type == INTR_TYPE_NS)); 232 return 1; 233 } 234 235 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 236 { 237 gicv3_set_interrupt_type(id, plat_my_core_pos(), type); 238 } 239 240 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 241 { 242 /* Target must be a valid MPIDR in the system */ 243 assert(plat_core_pos_by_mpidr(target) >= 0); 244 245 /* Verify that this is a secure EL3 SGI */ 246 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == 247 INTR_TYPE_EL3); 248 249 gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G0, target); 250 } 251 252 void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target) 253 { 254 /* Target must be a valid MPIDR in the system */ 255 assert(plat_core_pos_by_mpidr(target) >= 0); 256 257 /* Verify that this is a non-secure SGI */ 258 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == 259 INTR_TYPE_NS); 260 261 gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G1NS, target); 262 } 263 264 void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target) 265 { 266 /* Target must be a valid MPIDR in the system */ 267 assert(plat_core_pos_by_mpidr(target) >= 0); 268 269 /* Verify that this is a secure EL1 SGI */ 270 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == 271 INTR_TYPE_S_EL1); 272 273 gicv3_raise_sgi((unsigned int)sgi_num, GICV3_G1S, target); 274 } 275 276 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 277 u_register_t mpidr) 278 { 279 unsigned int irm = 0; 280 281 switch (routing_mode) { 282 case INTR_ROUTING_MODE_PE: 283 assert(plat_core_pos_by_mpidr(mpidr) >= 0); 284 irm = GICV3_IRM_PE; 285 break; 286 case INTR_ROUTING_MODE_ANY: 287 irm = GICV3_IRM_ANY; 288 break; 289 default: 290 assert(0); /* Unreachable */ 291 break; 292 } 293 294 gicv3_set_spi_routing(id, irm, mpidr); 295 } 296 297 void plat_ic_set_interrupt_pending(unsigned int id) 298 { 299 /* Disallow setting SGIs pending */ 300 assert(id >= MIN_PPI_ID); 301 gicv3_set_interrupt_pending(id, plat_my_core_pos()); 302 } 303 304 void plat_ic_clear_interrupt_pending(unsigned int id) 305 { 306 /* Disallow setting SGIs pending */ 307 assert(id >= MIN_PPI_ID); 308 gicv3_clear_interrupt_pending(id, plat_my_core_pos()); 309 } 310 311 unsigned int plat_ic_set_priority_mask(unsigned int mask) 312 { 313 return gicv3_set_pmr(mask); 314 } 315 316 unsigned int plat_ic_get_interrupt_id(unsigned int raw) 317 { 318 unsigned int id = raw & INT_ID_MASK; 319 320 return gicv3_is_intr_id_special_identifier(id) ? 321 INTR_ID_UNAVAILABLE : id; 322 } 323 #endif 324 #ifdef IMAGE_BL32 325 326 #pragma weak plat_ic_get_pending_interrupt_id 327 #pragma weak plat_ic_acknowledge_interrupt 328 #pragma weak plat_ic_end_of_interrupt 329 330 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 331 #ifndef __aarch64__ 332 #define IS_IN_EL1() IS_IN_SECURE() 333 #endif 334 335 /* 336 * This function returns the highest priority pending interrupt at 337 * the Interrupt controller 338 */ 339 uint32_t plat_ic_get_pending_interrupt_id(void) 340 { 341 unsigned int irqnr; 342 343 assert(IS_IN_EL1()); 344 irqnr = gicv3_get_pending_interrupt_id_sel1(); 345 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 346 INTR_ID_UNAVAILABLE : irqnr; 347 } 348 349 /* 350 * This function returns the highest priority pending interrupt at 351 * the Interrupt controller and indicates to the Interrupt controller 352 * that the interrupt processing has started. 353 */ 354 uint32_t plat_ic_acknowledge_interrupt(void) 355 { 356 assert(IS_IN_EL1()); 357 return gicv3_acknowledge_interrupt_sel1(); 358 } 359 360 /* 361 * This functions is used to indicate to the interrupt controller that 362 * the processing of the interrupt corresponding to the `id` has 363 * finished. 364 */ 365 void plat_ic_end_of_interrupt(uint32_t id) 366 { 367 assert(IS_IN_EL1()); 368 gicv3_end_of_interrupt_sel1(id); 369 } 370 #endif 371