1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 #include <stdbool.h> 15 16 #ifdef IMAGE_BL31 17 18 /* 19 * The following platform GIC functions are weakly defined. They 20 * provide typical implementations that may be re-used by multiple 21 * platforms but may also be overridden by a platform if required. 22 */ 23 #pragma weak plat_ic_get_pending_interrupt_id 24 #pragma weak plat_ic_get_pending_interrupt_type 25 #pragma weak plat_ic_acknowledge_interrupt 26 #pragma weak plat_ic_get_interrupt_type 27 #pragma weak plat_ic_end_of_interrupt 28 #pragma weak plat_interrupt_type_to_line 29 30 #pragma weak plat_ic_get_running_priority 31 #pragma weak plat_ic_is_spi 32 #pragma weak plat_ic_is_ppi 33 #pragma weak plat_ic_is_sgi 34 #pragma weak plat_ic_get_interrupt_active 35 #pragma weak plat_ic_enable_interrupt 36 #pragma weak plat_ic_disable_interrupt 37 #pragma weak plat_ic_set_interrupt_priority 38 #pragma weak plat_ic_set_interrupt_type 39 #pragma weak plat_ic_raise_el3_sgi 40 #pragma weak plat_ic_set_spi_routing 41 #pragma weak plat_ic_set_interrupt_pending 42 #pragma weak plat_ic_clear_interrupt_pending 43 44 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 45 (INTR_TYPE_NS == INTR_GROUP1NS) && 46 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 47 48 /* 49 * This function returns the highest priority pending interrupt at 50 * the Interrupt controller 51 */ 52 uint32_t plat_ic_get_pending_interrupt_id(void) 53 { 54 unsigned int irqnr; 55 56 assert(IS_IN_EL3()); 57 irqnr = gicv3_get_pending_interrupt_id(); 58 return gicv3_is_intr_id_special_identifier(irqnr) ? 59 INTR_ID_UNAVAILABLE : irqnr; 60 } 61 62 /* 63 * This function returns the type of the highest priority pending interrupt 64 * at the Interrupt controller. In the case of GICv3, the Highest Priority 65 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 66 * the id of the pending interrupt. The type of interrupt depends upon the 67 * id value as follows. 68 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 69 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 70 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 71 * type. 72 * 4. All other interrupt id's are reported as EL3 interrupt. 73 */ 74 uint32_t plat_ic_get_pending_interrupt_type(void) 75 { 76 unsigned int irqnr; 77 uint32_t type; 78 79 assert(IS_IN_EL3()); 80 irqnr = gicv3_get_pending_interrupt_type(); 81 82 switch (irqnr) { 83 case PENDING_G1S_INTID: 84 type = INTR_TYPE_S_EL1; 85 break; 86 case PENDING_G1NS_INTID: 87 type = INTR_TYPE_NS; 88 break; 89 case GIC_SPURIOUS_INTERRUPT: 90 type = INTR_TYPE_INVAL; 91 break; 92 default: 93 type = INTR_TYPE_EL3; 94 break; 95 } 96 97 return type; 98 } 99 100 /* 101 * This function returns the highest priority pending interrupt at 102 * the Interrupt controller and indicates to the Interrupt controller 103 * that the interrupt processing has started. 104 */ 105 uint32_t plat_ic_acknowledge_interrupt(void) 106 { 107 assert(IS_IN_EL3()); 108 return gicv3_acknowledge_interrupt(); 109 } 110 111 /* 112 * This function returns the type of the interrupt `id`, depending on how 113 * the interrupt has been configured in the interrupt controller 114 */ 115 uint32_t plat_ic_get_interrupt_type(uint32_t id) 116 { 117 assert(IS_IN_EL3()); 118 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 119 } 120 121 /* 122 * This functions is used to indicate to the interrupt controller that 123 * the processing of the interrupt corresponding to the `id` has 124 * finished. 125 */ 126 void plat_ic_end_of_interrupt(uint32_t id) 127 { 128 assert(IS_IN_EL3()); 129 gicv3_end_of_interrupt(id); 130 } 131 132 /* 133 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 134 * The interrupt controller knows which pin/line it uses to signal a type of 135 * interrupt. It lets the interrupt management framework determine for a type of 136 * interrupt and security state, which line should be used in the SCR_EL3 to 137 * control its routing to EL3. The interrupt line is represented as the bit 138 * position of the IRQ or FIQ bit in the SCR_EL3. 139 */ 140 uint32_t plat_interrupt_type_to_line(uint32_t type, 141 uint32_t security_state) 142 { 143 assert((type == INTR_TYPE_S_EL1) || 144 (type == INTR_TYPE_EL3) || 145 (type == INTR_TYPE_NS)); 146 147 assert(sec_state_is_valid(security_state)); 148 assert(IS_IN_EL3()); 149 150 switch (type) { 151 case INTR_TYPE_S_EL1: 152 /* 153 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 154 * and as FIQ in the NS-EL0/1/2 contexts 155 */ 156 if (security_state == SECURE) 157 return __builtin_ctz(SCR_IRQ_BIT); 158 else 159 return __builtin_ctz(SCR_FIQ_BIT); 160 assert(0); /* Unreachable */ 161 case INTR_TYPE_NS: 162 /* 163 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 164 * contexts and as IRQ in the NS-EL0/1/2 contexts. 165 */ 166 if (security_state == SECURE) 167 return __builtin_ctz(SCR_FIQ_BIT); 168 else 169 return __builtin_ctz(SCR_IRQ_BIT); 170 assert(0); /* Unreachable */ 171 case INTR_TYPE_EL3: 172 /* 173 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 174 * NS-EL0/1/2 contexts 175 */ 176 return __builtin_ctz(SCR_FIQ_BIT); 177 default: 178 panic(); 179 } 180 } 181 182 unsigned int plat_ic_get_running_priority(void) 183 { 184 return gicv3_get_running_priority(); 185 } 186 187 int plat_ic_is_spi(unsigned int id) 188 { 189 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 190 } 191 192 int plat_ic_is_ppi(unsigned int id) 193 { 194 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 195 } 196 197 int plat_ic_is_sgi(unsigned int id) 198 { 199 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 200 } 201 202 unsigned int plat_ic_get_interrupt_active(unsigned int id) 203 { 204 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 205 } 206 207 void plat_ic_enable_interrupt(unsigned int id) 208 { 209 gicv3_enable_interrupt(id, plat_my_core_pos()); 210 } 211 212 void plat_ic_disable_interrupt(unsigned int id) 213 { 214 gicv3_disable_interrupt(id, plat_my_core_pos()); 215 } 216 217 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 218 { 219 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); 220 } 221 222 int plat_ic_has_interrupt_type(unsigned int type) 223 { 224 assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || 225 (type == INTR_TYPE_NS)); 226 return 1; 227 } 228 229 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 230 { 231 gicv3_set_interrupt_type(id, plat_my_core_pos(), type); 232 } 233 234 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 235 { 236 /* Target must be a valid MPIDR in the system */ 237 assert(plat_core_pos_by_mpidr(target) >= 0); 238 239 /* Verify that this is a secure EL3 SGI */ 240 assert(plat_ic_get_interrupt_type((unsigned int)sgi_num) == 241 INTR_TYPE_EL3); 242 243 gicv3_raise_secure_g0_sgi((unsigned int)sgi_num, target); 244 } 245 246 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 247 u_register_t mpidr) 248 { 249 unsigned int irm = 0; 250 251 switch (routing_mode) { 252 case INTR_ROUTING_MODE_PE: 253 assert(plat_core_pos_by_mpidr(mpidr) >= 0); 254 irm = GICV3_IRM_PE; 255 break; 256 case INTR_ROUTING_MODE_ANY: 257 irm = GICV3_IRM_ANY; 258 break; 259 default: 260 assert(0); /* Unreachable */ 261 break; 262 } 263 264 gicv3_set_spi_routing(id, irm, mpidr); 265 } 266 267 void plat_ic_set_interrupt_pending(unsigned int id) 268 { 269 /* Disallow setting SGIs pending */ 270 assert(id >= MIN_PPI_ID); 271 gicv3_set_interrupt_pending(id, plat_my_core_pos()); 272 } 273 274 void plat_ic_clear_interrupt_pending(unsigned int id) 275 { 276 /* Disallow setting SGIs pending */ 277 assert(id >= MIN_PPI_ID); 278 gicv3_clear_interrupt_pending(id, plat_my_core_pos()); 279 } 280 281 unsigned int plat_ic_set_priority_mask(unsigned int mask) 282 { 283 return gicv3_set_pmr(mask); 284 } 285 286 unsigned int plat_ic_get_interrupt_id(unsigned int raw) 287 { 288 unsigned int id = raw & INT_ID_MASK; 289 290 return gicv3_is_intr_id_special_identifier(id) ? 291 INTR_ID_UNAVAILABLE : id; 292 } 293 #endif 294 #ifdef IMAGE_BL32 295 296 #pragma weak plat_ic_get_pending_interrupt_id 297 #pragma weak plat_ic_acknowledge_interrupt 298 #pragma weak plat_ic_end_of_interrupt 299 300 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 301 #ifdef AARCH32 302 #define IS_IN_EL1() IS_IN_SECURE() 303 #endif 304 305 /* 306 * This function returns the highest priority pending interrupt at 307 * the Interrupt controller 308 */ 309 uint32_t plat_ic_get_pending_interrupt_id(void) 310 { 311 unsigned int irqnr; 312 313 assert(IS_IN_EL1()); 314 irqnr = gicv3_get_pending_interrupt_id_sel1(); 315 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 316 INTR_ID_UNAVAILABLE : irqnr; 317 } 318 319 /* 320 * This function returns the highest priority pending interrupt at 321 * the Interrupt controller and indicates to the Interrupt controller 322 * that the interrupt processing has started. 323 */ 324 uint32_t plat_ic_acknowledge_interrupt(void) 325 { 326 assert(IS_IN_EL1()); 327 return gicv3_acknowledge_interrupt_sel1(); 328 } 329 330 /* 331 * This functions is used to indicate to the interrupt controller that 332 * the processing of the interrupt corresponding to the `id` has 333 * finished. 334 */ 335 void plat_ic_end_of_interrupt(uint32_t id) 336 { 337 assert(IS_IN_EL1()); 338 gicv3_end_of_interrupt_sel1(id); 339 } 340 #endif 341