1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <bl31/interrupt_mgmt.h> 11 #include <drivers/arm/gic_common.h> 12 #include <drivers/arm/gicv2.h> 13 #include <plat/common/platform.h> 14 15 /* 16 * The following platform GIC functions are weakly defined. They 17 * provide typical implementations that may be re-used by multiple 18 * platforms but may also be overridden by a platform if required. 19 */ 20 #pragma weak plat_ic_get_pending_interrupt_id 21 #pragma weak plat_ic_get_pending_interrupt_type 22 #pragma weak plat_ic_acknowledge_interrupt 23 #pragma weak plat_ic_get_interrupt_type 24 #pragma weak plat_ic_end_of_interrupt 25 #pragma weak plat_interrupt_type_to_line 26 27 #pragma weak plat_ic_get_running_priority 28 #pragma weak plat_ic_is_spi 29 #pragma weak plat_ic_is_ppi 30 #pragma weak plat_ic_is_sgi 31 #pragma weak plat_ic_get_interrupt_active 32 #pragma weak plat_ic_enable_interrupt 33 #pragma weak plat_ic_disable_interrupt 34 #pragma weak plat_ic_set_interrupt_priority 35 #pragma weak plat_ic_set_interrupt_type 36 #pragma weak plat_ic_raise_el3_sgi 37 #pragma weak plat_ic_set_spi_routing 38 39 /* 40 * This function returns the highest priority pending interrupt at 41 * the Interrupt controller 42 */ 43 uint32_t plat_ic_get_pending_interrupt_id(void) 44 { 45 unsigned int id; 46 47 id = gicv2_get_pending_interrupt_id(); 48 if (id == GIC_SPURIOUS_INTERRUPT) 49 return INTR_ID_UNAVAILABLE; 50 51 return id; 52 } 53 54 /* 55 * This function returns the type of the highest priority pending interrupt 56 * at the Interrupt controller. In the case of GICv2, the Highest Priority 57 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 58 * the pending interrupt. The type of interrupt depends upon the id value 59 * as follows. 60 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 61 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 62 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 63 * type. 64 */ 65 uint32_t plat_ic_get_pending_interrupt_type(void) 66 { 67 unsigned int id; 68 69 id = gicv2_get_pending_interrupt_type(); 70 71 /* Assume that all secure interrupts are S-EL1 interrupts */ 72 if (id < PENDING_G1_INTID) { 73 #if GICV2_G0_FOR_EL3 74 return INTR_TYPE_EL3; 75 #else 76 return INTR_TYPE_S_EL1; 77 #endif 78 } 79 80 if (id == GIC_SPURIOUS_INTERRUPT) 81 return INTR_TYPE_INVAL; 82 83 return INTR_TYPE_NS; 84 } 85 86 /* 87 * This function returns the highest priority pending interrupt at 88 * the Interrupt controller and indicates to the Interrupt controller 89 * that the interrupt processing has started. 90 */ 91 uint32_t plat_ic_acknowledge_interrupt(void) 92 { 93 return gicv2_acknowledge_interrupt(); 94 } 95 96 /* 97 * This function returns the type of the interrupt `id`, depending on how 98 * the interrupt has been configured in the interrupt controller 99 */ 100 uint32_t plat_ic_get_interrupt_type(uint32_t id) 101 { 102 unsigned int type; 103 104 type = gicv2_get_interrupt_group(id); 105 106 /* Assume that all secure interrupts are S-EL1 interrupts */ 107 return (type == GICV2_INTR_GROUP1) ? INTR_TYPE_NS : 108 #if GICV2_G0_FOR_EL3 109 INTR_TYPE_EL3; 110 #else 111 INTR_TYPE_S_EL1; 112 #endif 113 } 114 115 /* 116 * This functions is used to indicate to the interrupt controller that 117 * the processing of the interrupt corresponding to the `id` has 118 * finished. 119 */ 120 void plat_ic_end_of_interrupt(uint32_t id) 121 { 122 gicv2_end_of_interrupt(id); 123 } 124 125 /* 126 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 127 * The interrupt controller knows which pin/line it uses to signal a type of 128 * interrupt. It lets the interrupt management framework determine 129 * for a type of interrupt and security state, which line should be used in the 130 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 131 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 132 */ 133 uint32_t plat_interrupt_type_to_line(uint32_t type, 134 uint32_t security_state) 135 { 136 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || 137 (type == INTR_TYPE_NS)); 138 139 assert(sec_state_is_valid(security_state)); 140 141 /* Non-secure interrupts are signaled on the IRQ line always */ 142 if (type == INTR_TYPE_NS) 143 return __builtin_ctz(SCR_IRQ_BIT); 144 145 /* 146 * Secure interrupts are signaled using the IRQ line if the FIQ is 147 * not enabled else they are signaled using the FIQ line. 148 */ 149 return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) : 150 __builtin_ctz(SCR_IRQ_BIT)); 151 } 152 153 unsigned int plat_ic_get_running_priority(void) 154 { 155 return gicv2_get_running_priority(); 156 } 157 158 int plat_ic_is_spi(unsigned int id) 159 { 160 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 161 } 162 163 int plat_ic_is_ppi(unsigned int id) 164 { 165 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 166 } 167 168 int plat_ic_is_sgi(unsigned int id) 169 { 170 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 171 } 172 173 unsigned int plat_ic_get_interrupt_active(unsigned int id) 174 { 175 return gicv2_get_interrupt_active(id); 176 } 177 178 void plat_ic_enable_interrupt(unsigned int id) 179 { 180 gicv2_enable_interrupt(id); 181 } 182 183 void plat_ic_disable_interrupt(unsigned int id) 184 { 185 gicv2_disable_interrupt(id); 186 } 187 188 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 189 { 190 gicv2_set_interrupt_priority(id, priority); 191 } 192 193 int plat_ic_has_interrupt_type(unsigned int type) 194 { 195 int has_interrupt_type = 0; 196 197 switch (type) { 198 #if GICV2_G0_FOR_EL3 199 case INTR_TYPE_EL3: 200 #else 201 case INTR_TYPE_S_EL1: 202 #endif 203 case INTR_TYPE_NS: 204 has_interrupt_type = 1; 205 break; 206 default: 207 /* Do nothing in default case */ 208 break; 209 } 210 211 return has_interrupt_type; 212 } 213 214 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 215 { 216 unsigned int gicv2_type = 0U; 217 218 /* Map canonical interrupt type to GICv2 type */ 219 switch (type) { 220 #if GICV2_G0_FOR_EL3 221 case INTR_TYPE_EL3: 222 #else 223 case INTR_TYPE_S_EL1: 224 #endif 225 gicv2_type = GICV2_INTR_GROUP0; 226 break; 227 case INTR_TYPE_NS: 228 gicv2_type = GICV2_INTR_GROUP1; 229 break; 230 default: 231 assert(0); /* Unreachable */ 232 break; 233 } 234 235 gicv2_set_interrupt_type(id, gicv2_type); 236 } 237 238 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 239 { 240 #if GICV2_G0_FOR_EL3 241 int id; 242 243 /* Target must be a valid MPIDR in the system */ 244 id = plat_core_pos_by_mpidr(target); 245 assert(id >= 0); 246 247 /* Verify that this is a secure SGI */ 248 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 249 250 gicv2_raise_sgi(sgi_num, id); 251 #else 252 assert(false); 253 #endif 254 } 255 256 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 257 u_register_t mpidr) 258 { 259 int proc_num = 0; 260 261 switch (routing_mode) { 262 case INTR_ROUTING_MODE_PE: 263 proc_num = plat_core_pos_by_mpidr(mpidr); 264 assert(proc_num >= 0); 265 break; 266 case INTR_ROUTING_MODE_ANY: 267 /* Bit mask selecting all 8 CPUs as candidates */ 268 proc_num = -1; 269 break; 270 default: 271 assert(0); /* Unreachable */ 272 break; 273 } 274 275 gicv2_set_spi_routing(id, proc_num); 276 } 277 278 void plat_ic_set_interrupt_pending(unsigned int id) 279 { 280 gicv2_set_interrupt_pending(id); 281 } 282 283 void plat_ic_clear_interrupt_pending(unsigned int id) 284 { 285 gicv2_clear_interrupt_pending(id); 286 } 287 288 unsigned int plat_ic_set_priority_mask(unsigned int mask) 289 { 290 return gicv2_set_pmr(mask); 291 } 292 293 unsigned int plat_ic_get_interrupt_id(unsigned int raw) 294 { 295 unsigned int id = (raw & INT_ID_MASK); 296 297 if (id == GIC_SPURIOUS_INTERRUPT) 298 id = INTR_ID_UNAVAILABLE; 299 300 return id; 301 } 302