1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 11 #include <bl31/interrupt_mgmt.h> 12 #include <drivers/arm/gic_common.h> 13 #include <drivers/arm/gicv2.h> 14 #include <plat/common/platform.h> 15 16 /* 17 * The following platform GIC functions are weakly defined. They 18 * provide typical implementations that may be re-used by multiple 19 * platforms but may also be overridden by a platform if required. 20 */ 21 #pragma weak plat_ic_get_pending_interrupt_id 22 #pragma weak plat_ic_get_pending_interrupt_type 23 #pragma weak plat_ic_acknowledge_interrupt 24 #pragma weak plat_ic_get_interrupt_type 25 #pragma weak plat_ic_end_of_interrupt 26 #pragma weak plat_interrupt_type_to_line 27 28 #pragma weak plat_ic_get_running_priority 29 #pragma weak plat_ic_is_spi 30 #pragma weak plat_ic_is_ppi 31 #pragma weak plat_ic_is_sgi 32 #pragma weak plat_ic_get_interrupt_active 33 #pragma weak plat_ic_enable_interrupt 34 #pragma weak plat_ic_disable_interrupt 35 #pragma weak plat_ic_set_interrupt_priority 36 #pragma weak plat_ic_set_interrupt_type 37 #pragma weak plat_ic_raise_el3_sgi 38 #pragma weak plat_ic_raise_ns_sgi 39 #pragma weak plat_ic_raise_s_el1_sgi 40 #pragma weak plat_ic_set_spi_routing 41 42 /* 43 * This function returns the highest priority pending interrupt at 44 * the Interrupt controller 45 */ 46 uint32_t plat_ic_get_pending_interrupt_id(void) 47 { 48 unsigned int id; 49 50 id = gicv2_get_pending_interrupt_id(); 51 if (id == GIC_SPURIOUS_INTERRUPT) { 52 id = INTR_ID_UNAVAILABLE; 53 } 54 55 return id; 56 } 57 58 /* 59 * This function returns the type of the highest priority pending interrupt 60 * at the Interrupt controller. In the case of GICv2, the Highest Priority 61 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 62 * the pending interrupt. The type of interrupt depends upon the id value 63 * as follows. 64 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 65 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 66 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 67 * type. 68 */ 69 uint32_t plat_ic_get_pending_interrupt_type(void) 70 { 71 unsigned int id; 72 uint32_t interrupt_type; 73 74 id = gicv2_get_pending_interrupt_type(); 75 76 /* Assume that all secure interrupts are S-EL1 interrupts */ 77 if (id < PENDING_G1_INTID) { 78 #if GICV2_G0_FOR_EL3 79 interrupt_type = INTR_TYPE_EL3; 80 #else 81 interrupt_type = INTR_TYPE_S_EL1; 82 #endif 83 } else { 84 85 if (id == GIC_SPURIOUS_INTERRUPT) { 86 interrupt_type = INTR_TYPE_INVAL; 87 } else { 88 interrupt_type = INTR_TYPE_NS; 89 } 90 } 91 92 return interrupt_type; 93 } 94 95 /* 96 * This function returns the highest priority pending interrupt at 97 * the Interrupt controller and indicates to the Interrupt controller 98 * that the interrupt processing has started. 99 */ 100 uint32_t plat_ic_acknowledge_interrupt(void) 101 { 102 return gicv2_acknowledge_interrupt(); 103 } 104 105 /* 106 * This function returns the type of the interrupt `id`, depending on how 107 * the interrupt has been configured in the interrupt controller 108 */ 109 uint32_t plat_ic_get_interrupt_type(uint32_t id) 110 { 111 unsigned int type; 112 113 type = gicv2_get_interrupt_group(id); 114 115 /* Assume that all secure interrupts are S-EL1 interrupts */ 116 return (type == GICV2_INTR_GROUP1) ? INTR_TYPE_NS : 117 #if GICV2_G0_FOR_EL3 118 INTR_TYPE_EL3; 119 #else 120 INTR_TYPE_S_EL1; 121 #endif 122 } 123 124 /* 125 * This functions is used to indicate to the interrupt controller that 126 * the processing of the interrupt corresponding to the `id` has 127 * finished. 128 */ 129 void plat_ic_end_of_interrupt(uint32_t id) 130 { 131 gicv2_end_of_interrupt(id); 132 } 133 134 /* 135 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 136 * The interrupt controller knows which pin/line it uses to signal a type of 137 * interrupt. It lets the interrupt management framework determine 138 * for a type of interrupt and security state, which line should be used in the 139 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 140 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 141 */ 142 uint32_t plat_interrupt_type_to_line(uint32_t type, 143 uint32_t security_state) 144 { 145 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || 146 (type == INTR_TYPE_NS)); 147 148 assert(sec_state_is_valid(security_state)); 149 150 /* Non-secure interrupts are signaled on the IRQ line always */ 151 if (type == INTR_TYPE_NS) { 152 return __builtin_ctz(SCR_IRQ_BIT); 153 } 154 155 /* 156 * Secure interrupts are signaled using the IRQ line if the FIQ is 157 * not enabled else they are signaled using the FIQ line. 158 */ 159 return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) : 160 __builtin_ctz(SCR_IRQ_BIT)); 161 } 162 163 unsigned int plat_ic_get_running_priority(void) 164 { 165 return gicv2_get_running_priority(); 166 } 167 168 int plat_ic_is_spi(unsigned int id) 169 { 170 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 171 } 172 173 int plat_ic_is_ppi(unsigned int id) 174 { 175 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 176 } 177 178 int plat_ic_is_sgi(unsigned int id) 179 { 180 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 181 } 182 183 unsigned int plat_ic_get_interrupt_active(unsigned int id) 184 { 185 return gicv2_get_interrupt_active(id); 186 } 187 188 void plat_ic_enable_interrupt(unsigned int id) 189 { 190 gicv2_enable_interrupt(id); 191 } 192 193 void plat_ic_disable_interrupt(unsigned int id) 194 { 195 gicv2_disable_interrupt(id); 196 } 197 198 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 199 { 200 gicv2_set_interrupt_priority(id, priority); 201 } 202 203 bool plat_ic_has_interrupt_type(unsigned int type) 204 { 205 bool has_interrupt_type = false; 206 207 switch (type) { 208 #if GICV2_G0_FOR_EL3 209 case INTR_TYPE_EL3: 210 #else 211 case INTR_TYPE_S_EL1: 212 #endif 213 case INTR_TYPE_NS: 214 has_interrupt_type = true; 215 break; 216 default: 217 /* Do nothing in default case */ 218 break; 219 } 220 221 return has_interrupt_type; 222 } 223 224 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 225 { 226 unsigned int gicv2_group = 0U; 227 228 /* Map canonical interrupt type to GICv2 type */ 229 switch (type) { 230 #if GICV2_G0_FOR_EL3 231 case INTR_TYPE_EL3: 232 #else 233 case INTR_TYPE_S_EL1: 234 #endif 235 gicv2_group = GICV2_INTR_GROUP0; 236 break; 237 case INTR_TYPE_NS: 238 gicv2_group = GICV2_INTR_GROUP1; 239 break; 240 default: 241 assert(false); /* Unreachable */ 242 break; 243 } 244 245 gicv2_set_interrupt_group(id, gicv2_group); 246 } 247 248 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 249 { 250 #if GICV2_G0_FOR_EL3 251 int id; 252 253 /* Target must be a valid MPIDR in the system */ 254 id = plat_core_pos_by_mpidr(target); 255 assert(id >= 0); 256 257 /* Verify that this is a secure SGI */ 258 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 259 260 gicv2_raise_sgi(sgi_num, false, id); 261 #else 262 assert(false); 263 #endif 264 } 265 266 void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target) 267 { 268 int id; 269 270 /* Target must be a valid MPIDR in the system */ 271 id = plat_core_pos_by_mpidr(target); 272 assert(id >= 0); 273 274 /* Verify that this is a non-secure SGI */ 275 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_NS); 276 277 gicv2_raise_sgi(sgi_num, true, id); 278 } 279 280 void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target) 281 { 282 #if GICV2_G0_FOR_EL3 283 assert(false); 284 #else 285 int id; 286 287 /* Target must be a valid MPIDR in the system */ 288 id = plat_core_pos_by_mpidr(target); 289 assert(id >= 0); 290 291 /* Verify that this is a secure EL1 SGI */ 292 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_S_EL1); 293 294 gicv2_raise_sgi(sgi_num, false, id); 295 #endif 296 } 297 298 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 299 u_register_t mpidr) 300 { 301 int proc_num = 0; 302 303 switch (routing_mode) { 304 case INTR_ROUTING_MODE_PE: 305 proc_num = plat_core_pos_by_mpidr(mpidr); 306 assert(proc_num >= 0); 307 break; 308 case INTR_ROUTING_MODE_ANY: 309 /* Bit mask selecting all 8 CPUs as candidates */ 310 proc_num = -1; 311 break; 312 default: 313 assert(0); /* Unreachable */ 314 break; 315 } 316 317 gicv2_set_spi_routing(id, proc_num); 318 } 319 320 void plat_ic_set_interrupt_pending(unsigned int id) 321 { 322 gicv2_set_interrupt_pending(id); 323 } 324 325 void plat_ic_clear_interrupt_pending(unsigned int id) 326 { 327 gicv2_clear_interrupt_pending(id); 328 } 329 330 unsigned int plat_ic_set_priority_mask(unsigned int mask) 331 { 332 return gicv2_set_pmr(mask); 333 } 334 335 unsigned int plat_ic_get_interrupt_id(unsigned int raw) 336 { 337 unsigned int id = (raw & INT_ID_MASK); 338 339 if (id == GIC_SPURIOUS_INTERRUPT) { 340 id = INTR_ID_UNAVAILABLE; 341 } 342 343 return id; 344 } 345