1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <platform.h> 33 34 35 .globl pcpu_dv_mem_stack 36 .weak platform_get_core_pos 37 .weak platform_set_stack 38 .weak platform_get_stack 39 .weak platform_is_primary_cpu 40 .weak platform_set_coherent_stack 41 .weak platform_check_mpidr 42 .weak plat_report_exception 43 44 /* ----------------------------------------------------- 45 * Coherent stack sizes for debug and release builds 46 * ----------------------------------------------------- 47 */ 48#if DEBUG 49#define PCPU_DV_MEM_STACK_SIZE 0x400 50#else 51#define PCPU_DV_MEM_STACK_SIZE 0x300 52#endif 53 54 .section .text, "ax"; .align 3 55 56 /* ----------------------------------------------------- 57 * unsigned long long platform_set_coherent_stack 58 * (unsigned mpidr); 59 * For a given mpidr, this function returns the stack 60 * pointer allocated in device memory. This stack can 61 * be used by C code which enables/disables the SCTLR.M 62 * SCTLR.C bit e.g. while powering down a cpu 63 * ----------------------------------------------------- 64 */ 65platform_set_coherent_stack: ; .type platform_set_coherent_stack, %function 66 mov x5, x30 // lr 67 bl platform_get_core_pos 68 add x0, x0, #1 69 mov x1, #PCPU_DV_MEM_STACK_SIZE 70 mul x0, x0, x1 71 ldr x1, =pcpu_dv_mem_stack 72 add sp, x1, x0 73 ret x5 74 75 76 /* ----------------------------------------------------- 77 * int platform_get_core_pos(int mpidr); 78 * With this function: CorePos = (ClusterId * 4) + 79 * CoreId 80 * ----------------------------------------------------- 81 */ 82platform_get_core_pos: ; .type platform_get_core_pos, %function 83 and x1, x0, #MPIDR_CPU_MASK 84 and x0, x0, #MPIDR_CLUSTER_MASK 85 add x0, x1, x0, LSR #6 86 ret 87 88 89 /* ----------------------------------------------------- 90 * void platform_is_primary_cpu (unsigned int mpid); 91 * 92 * Given the mpidr say whether this cpu is the primary 93 * cpu (applicable ony after a cold boot) 94 * ----------------------------------------------------- 95 */ 96platform_is_primary_cpu: ; .type platform_is_primary_cpu, %function 97 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 98 cmp x0, #PRIMARY_CPU 99 cset x0, eq 100 ret 101 102 /* ----------------------------------------------------- 103 * void platform_get_stack (unsigned long mpidr) 104 * ----------------------------------------------------- 105 */ 106platform_get_stack: ; .type platform_get_stack, %function 107 mov x10, x30 // lr 108 bl platform_get_core_pos 109 add x0, x0, #1 110 mov x1, #PLATFORM_STACK_SIZE 111 mul x0, x0, x1 112 ldr x1, =platform_normal_stacks 113 add x0, x1, x0 114 ret x10 115 116 /* ----------------------------------------------------- 117 * void platform_set_stack (unsigned long mpidr) 118 * ----------------------------------------------------- 119 */ 120platform_set_stack: ; .type platform_set_stack, %function 121 mov x9, x30 // lr 122 bl platform_get_stack 123 mov sp, x0 124 ret x9 125 126 /* ----------------------------------------------------- 127 * Placeholder function which should be redefined by 128 * each platform. 129 * ----------------------------------------------------- 130 */ 131platform_check_mpidr: ; .type platform_check_mpidr, %function 132 mov x0, xzr 133 ret 134 135 /* ----------------------------------------------------- 136 * Placeholder function which should be redefined by 137 * each platform. 138 * ----------------------------------------------------- 139 */ 140plat_report_exception: 141 ret 142 143 /* ----------------------------------------------------- 144 * Per-cpu stacks in device memory. 145 * Used for C code just before power down or right after 146 * power up when the MMU or caches need to be turned on 147 * or off. Each cpu gets a stack of 512 bytes. 148 * ----------------------------------------------------- 149 */ 150 .section tzfw_coherent_mem, "aw", %nobits; .align 6 151 152pcpu_dv_mem_stack: 153 /* Zero fill */ 154 .space (PLATFORM_CORE_COUNT * PCPU_DV_MEM_STACK_SIZE), 0 155