1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <console.h> 10#include <platform_def.h> 11 12 .weak plat_report_exception 13 .weak plat_crash_console_init 14 .weak plat_crash_console_putc 15 .weak plat_crash_console_flush 16 .weak plat_reset_handler 17 .weak plat_disable_acp 18 .weak bl1_plat_prepare_exit 19 .weak plat_panic_handler 20 .weak bl31_plat_enable_mmu 21 .weak bl32_plat_enable_mmu 22 23 .weak plat_handle_uncontainable_ea 24 .weak plat_handle_double_fault 25 .weak plat_handle_el3_ea 26 27#if !ENABLE_PLAT_COMPAT 28 .globl platform_get_core_pos 29 30#define MPIDR_RES_BIT_MASK 0xff000000 31 32 /* ------------------------------------------------------------------ 33 * int platform_get_core_pos(int mpidr) 34 * Returns the CPU index of the CPU specified by mpidr. This is 35 * defined when platform compatibility is disabled to enable Trusted 36 * Firmware components like SPD using the old platform API to work. 37 * This API is deprecated and it assumes that the mpidr specified is 38 * that of a valid and present CPU. Instead, plat_my_core_pos() 39 * should be used for CPU index of the current CPU and 40 * plat_core_pos_by_mpidr() should be used for CPU index of a 41 * CPU specified by its mpidr. 42 * ------------------------------------------------------------------ 43 */ 44func_deprecated platform_get_core_pos 45 bic x0, x0, #MPIDR_RES_BIT_MASK 46 mrs x1, mpidr_el1 47 bic x1, x1, #MPIDR_RES_BIT_MASK 48 cmp x0, x1 49 beq plat_my_core_pos 50 b platform_core_pos_helper 51endfunc_deprecated platform_get_core_pos 52#endif 53 54 /* ----------------------------------------------------- 55 * Placeholder function which should be redefined by 56 * each platform. 57 * ----------------------------------------------------- 58 */ 59func plat_report_exception 60 ret 61endfunc plat_report_exception 62 63#if MULTI_CONSOLE_API 64 /* ----------------------------------------------------- 65 * int plat_crash_console_init(void) 66 * Use normal console by default. Switch it to crash 67 * mode so serial consoles become active again. 68 * NOTE: This default implementation will only work for 69 * crashes that occur after a normal console (marked 70 * valid for the crash state) has been registered with 71 * the console framework. To debug crashes that occur 72 * earlier, the platform has to override these functions 73 * with an implementation that initializes a console 74 * driver with hardcoded parameters. See 75 * docs/porting-guide.rst for more information. 76 * ----------------------------------------------------- 77 */ 78func plat_crash_console_init 79#if defined(IMAGE_BL1) 80 /* 81 * BL1 code can possibly crash so early that the data segment is not yet 82 * accessible. Don't risk undefined behavior by trying to run the normal 83 * console framework. Platforms that want to debug BL1 will need to 84 * override this with custom functions that can run from registers only. 85 */ 86 mov x0, #0 87 ret 88#else /* IMAGE_BL1 */ 89 mov x3, x30 90 mov x0, #CONSOLE_FLAG_CRASH 91 bl console_switch_state 92 mov x0, #1 93 ret x3 94#endif 95endfunc plat_crash_console_init 96 97 /* ----------------------------------------------------- 98 * void plat_crash_console_putc(int character) 99 * Output through the normal console by default. 100 * ----------------------------------------------------- 101 */ 102func plat_crash_console_putc 103 b console_putc 104endfunc plat_crash_console_putc 105 106 /* ----------------------------------------------------- 107 * void plat_crash_console_flush(void) 108 * Flush normal console by default. 109 * ----------------------------------------------------- 110 */ 111func plat_crash_console_flush 112 b console_flush 113endfunc plat_crash_console_flush 114 115#else /* MULTI_CONSOLE_API */ 116 117 /* ----------------------------------------------------- 118 * In the old API these are all no-op stubs that need to 119 * be overridden by the platform to be useful. 120 * ----------------------------------------------------- 121 */ 122func plat_crash_console_init 123 mov x0, #0 124 ret 125endfunc plat_crash_console_init 126 127func plat_crash_console_putc 128 ret 129endfunc plat_crash_console_putc 130 131func plat_crash_console_flush 132 ret 133endfunc plat_crash_console_flush 134#endif 135 136 /* ----------------------------------------------------- 137 * Placeholder function which should be redefined by 138 * each platform. This function should preserve x19 - x29. 139 * ----------------------------------------------------- 140 */ 141func plat_reset_handler 142 ret 143endfunc plat_reset_handler 144 145 /* ----------------------------------------------------- 146 * Placeholder function which should be redefined by 147 * each platform. This function is allowed to use 148 * registers x0 - x17. 149 * ----------------------------------------------------- 150 */ 151func plat_disable_acp 152 ret 153endfunc plat_disable_acp 154 155 /* ----------------------------------------------------- 156 * void bl1_plat_prepare_exit(entry_point_info_t *ep_info); 157 * Called before exiting BL1. Default: do nothing 158 * ----------------------------------------------------- 159 */ 160func bl1_plat_prepare_exit 161 ret 162endfunc bl1_plat_prepare_exit 163 164 /* ----------------------------------------------------- 165 * void plat_panic_handler(void) __dead2; 166 * Endless loop by default. 167 * ----------------------------------------------------- 168 */ 169func plat_panic_handler 170 wfi 171 b plat_panic_handler 172endfunc plat_panic_handler 173 174 /* ----------------------------------------------------- 175 * void bl31_plat_enable_mmu(uint32_t flags); 176 * 177 * Enable MMU in BL31. 178 * ----------------------------------------------------- 179 */ 180func bl31_plat_enable_mmu 181 b enable_mmu_direct_el3 182endfunc bl31_plat_enable_mmu 183 184 /* ----------------------------------------------------- 185 * void bl32_plat_enable_mmu(uint32_t flags); 186 * 187 * Enable MMU in BL32. 188 * ----------------------------------------------------- 189 */ 190func bl32_plat_enable_mmu 191 b enable_mmu_direct_el1 192endfunc bl32_plat_enable_mmu 193 194 195 /* ----------------------------------------------------- 196 * Platform handler for Uncontainable External Abort. 197 * 198 * x0: EA reason 199 * x1: EA syndrome 200 * ----------------------------------------------------- 201 */ 202func plat_handle_uncontainable_ea 203 b report_unhandled_exception 204endfunc plat_handle_uncontainable_ea 205 206 /* ----------------------------------------------------- 207 * Platform handler for Double Fault. 208 * 209 * x0: EA reason 210 * x1: EA syndrome 211 * ----------------------------------------------------- 212 */ 213func plat_handle_double_fault 214 b report_unhandled_exception 215endfunc plat_handle_double_fault 216 217 /* ----------------------------------------------------- 218 * Platform handler for EL3 External Abort. 219 * ----------------------------------------------------- 220 */ 221func plat_handle_el3_ea 222 b report_unhandled_exception 223endfunc plat_handle_el3_ea 224