1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <platform.h> 33#include <asm_macros.S> 34 35 36 .globl pcpu_dv_mem_stack 37 .weak platform_get_core_pos 38 .weak platform_set_stack 39 .weak platform_get_stack 40 .weak platform_is_primary_cpu 41 .weak platform_set_coherent_stack 42 .weak platform_check_mpidr 43 .weak plat_report_exception 44 45 /* ----------------------------------------------------- 46 * Coherent stack sizes for debug and release builds 47 * ----------------------------------------------------- 48 */ 49#if DEBUG 50#define PCPU_DV_MEM_STACK_SIZE 0x400 51#else 52#define PCPU_DV_MEM_STACK_SIZE 0x300 53#endif 54 55 /* ----------------------------------------------------- 56 * unsigned long long platform_set_coherent_stack 57 * (unsigned mpidr); 58 * For a given mpidr, this function returns the stack 59 * pointer allocated in device memory. This stack can 60 * be used by C code which enables/disables the SCTLR.M 61 * SCTLR.C bit e.g. while powering down a cpu 62 * ----------------------------------------------------- 63 */ 64func platform_set_coherent_stack 65 mov x5, x30 // lr 66 bl platform_get_core_pos 67 add x0, x0, #1 68 mov x1, #PCPU_DV_MEM_STACK_SIZE 69 mul x0, x0, x1 70 ldr x1, =pcpu_dv_mem_stack 71 add sp, x1, x0 72 ret x5 73 74 75 /* ----------------------------------------------------- 76 * int platform_get_core_pos(int mpidr); 77 * With this function: CorePos = (ClusterId * 4) + 78 * CoreId 79 * ----------------------------------------------------- 80 */ 81func platform_get_core_pos 82 and x1, x0, #MPIDR_CPU_MASK 83 and x0, x0, #MPIDR_CLUSTER_MASK 84 add x0, x1, x0, LSR #6 85 ret 86 87 88 /* ----------------------------------------------------- 89 * void platform_is_primary_cpu (unsigned int mpid); 90 * 91 * Given the mpidr say whether this cpu is the primary 92 * cpu (applicable ony after a cold boot) 93 * ----------------------------------------------------- 94 */ 95func platform_is_primary_cpu 96 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 97 cmp x0, #PRIMARY_CPU 98 cset x0, eq 99 ret 100 101 /* ----------------------------------------------------- 102 * void platform_get_stack (unsigned long mpidr) 103 * ----------------------------------------------------- 104 */ 105func platform_get_stack 106 mov x10, x30 // lr 107 bl platform_get_core_pos 108 add x0, x0, #1 109 mov x1, #PLATFORM_STACK_SIZE 110 mul x0, x0, x1 111 ldr x1, =platform_normal_stacks 112 add x0, x1, x0 113 ret x10 114 115 /* ----------------------------------------------------- 116 * void platform_set_stack (unsigned long mpidr) 117 * ----------------------------------------------------- 118 */ 119func platform_set_stack 120 mov x9, x30 // lr 121 bl platform_get_stack 122 mov sp, x0 123 ret x9 124 125 /* ----------------------------------------------------- 126 * Placeholder function which should be redefined by 127 * each platform. 128 * ----------------------------------------------------- 129 */ 130func platform_check_mpidr 131 mov x0, xzr 132 ret 133 134 /* ----------------------------------------------------- 135 * Placeholder function which should be redefined by 136 * each platform. 137 * ----------------------------------------------------- 138 */ 139func plat_report_exception 140 ret 141 142 /* ----------------------------------------------------- 143 * Per-cpu stacks in device memory. 144 * Used for C code just before power down or right after 145 * power up when the MMU or caches need to be turned on 146 * or off. Each cpu gets a stack of 512 bytes. 147 * ----------------------------------------------------- 148 */ 149 .section tzfw_coherent_mem, "aw", %nobits; .align 6 150 151pcpu_dv_mem_stack: 152 /* Zero fill */ 153 .space (PLATFORM_CORE_COUNT * PCPU_DV_MEM_STACK_SIZE), 0 154