xref: /rk3399_ARM-atf/plat/common/aarch64/platform_helpers.S (revision 4f6ad66ae9fcc8bcb3b0fcee10b7ab1ffcaf1a56)
1*4f6ad66aSAchin Gupta/*
2*4f6ad66aSAchin Gupta * Copyright (c) 2013, ARM Limited. All rights reserved.
3*4f6ad66aSAchin Gupta *
4*4f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without
5*4f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met:
6*4f6ad66aSAchin Gupta *
7*4f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this
8*4f6ad66aSAchin Gupta * list of conditions and the following disclaimer.
9*4f6ad66aSAchin Gupta *
10*4f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice,
11*4f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation
12*4f6ad66aSAchin Gupta * and/or other materials provided with the distribution.
13*4f6ad66aSAchin Gupta *
14*4f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used
15*4f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific
16*4f6ad66aSAchin Gupta * prior written permission.
17*4f6ad66aSAchin Gupta *
18*4f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19*4f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20*4f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21*4f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22*4f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23*4f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24*4f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25*4f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26*4f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27*4f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28*4f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE.
29*4f6ad66aSAchin Gupta */
30*4f6ad66aSAchin Gupta
31*4f6ad66aSAchin Gupta#include <arch.h>
32*4f6ad66aSAchin Gupta#include <platform.h>
33*4f6ad66aSAchin Gupta
34*4f6ad66aSAchin Gupta
35*4f6ad66aSAchin Gupta	.globl	pcpu_dv_mem_stack
36*4f6ad66aSAchin Gupta	.weak	platform_get_core_pos
37*4f6ad66aSAchin Gupta	.weak	platform_set_stack
38*4f6ad66aSAchin Gupta	.weak	platform_is_primary_cpu
39*4f6ad66aSAchin Gupta	.weak	platform_set_coherent_stack
40*4f6ad66aSAchin Gupta	.weak	platform_check_mpidr
41*4f6ad66aSAchin Gupta	.weak	plat_report_exception
42*4f6ad66aSAchin Gupta
43*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
44*4f6ad66aSAchin Gupta	 * 512 bytes of coherent stack for each cpu
45*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
46*4f6ad66aSAchin Gupta	 */
47*4f6ad66aSAchin Gupta#define PCPU_DV_MEM_STACK_SIZE	0x200
48*4f6ad66aSAchin Gupta
49*4f6ad66aSAchin Gupta
50*4f6ad66aSAchin Gupta	.section	.text, "ax"; .align 3
51*4f6ad66aSAchin Gupta
52*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
53*4f6ad66aSAchin Gupta	 * unsigned long long platform_set_coherent_stack
54*4f6ad66aSAchin Gupta	 *                                    (unsigned mpidr);
55*4f6ad66aSAchin Gupta	 * For a given mpidr, this function returns the stack
56*4f6ad66aSAchin Gupta	 * pointer allocated in device memory. This stack can
57*4f6ad66aSAchin Gupta	 * be used by C code which enables/disables the SCTLR.M
58*4f6ad66aSAchin Gupta	 * SCTLR.C bit e.g. while powering down a cpu
59*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
60*4f6ad66aSAchin Gupta	 */
61*4f6ad66aSAchin Guptaplatform_set_coherent_stack:; .type platform_set_coherent_stack, %function
62*4f6ad66aSAchin Gupta	mov	x5, x30 // lr
63*4f6ad66aSAchin Gupta	bl	platform_get_core_pos
64*4f6ad66aSAchin Gupta	add	x0, x0, #1
65*4f6ad66aSAchin Gupta	mov	x1, #PCPU_DV_MEM_STACK_SIZE
66*4f6ad66aSAchin Gupta	mul	x0, x0, x1
67*4f6ad66aSAchin Gupta	ldr	x1, =pcpu_dv_mem_stack
68*4f6ad66aSAchin Gupta	add	sp, x1, x0
69*4f6ad66aSAchin Gupta	ret	x5
70*4f6ad66aSAchin Gupta
71*4f6ad66aSAchin Gupta
72*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
73*4f6ad66aSAchin Gupta	 *  int platform_get_core_pos(int mpidr);
74*4f6ad66aSAchin Gupta	 *  With this function: CorePos = (ClusterId * 4) +
75*4f6ad66aSAchin Gupta	 *  				  CoreId
76*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
77*4f6ad66aSAchin Gupta	 */
78*4f6ad66aSAchin Guptaplatform_get_core_pos:; .type platform_get_core_pos, %function
79*4f6ad66aSAchin Gupta	and	x1, x0, #MPIDR_CPU_MASK
80*4f6ad66aSAchin Gupta	and	x0, x0, #MPIDR_CLUSTER_MASK
81*4f6ad66aSAchin Gupta	add	x0, x1, x0, LSR #6
82*4f6ad66aSAchin Gupta	ret
83*4f6ad66aSAchin Gupta
84*4f6ad66aSAchin Gupta
85*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
86*4f6ad66aSAchin Gupta	 * void platform_is_primary_cpu (unsigned int mpid);
87*4f6ad66aSAchin Gupta	 *
88*4f6ad66aSAchin Gupta	 * Given the mpidr say whether this cpu is the primary
89*4f6ad66aSAchin Gupta	 * cpu (applicable ony after a cold boot)
90*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
91*4f6ad66aSAchin Gupta	 */
92*4f6ad66aSAchin Guptaplatform_is_primary_cpu:; .type platform_is_primary_cpu, %function
93*4f6ad66aSAchin Gupta	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
94*4f6ad66aSAchin Gupta	cmp	x0, #PRIMARY_CPU
95*4f6ad66aSAchin Gupta	cset	x0, eq
96*4f6ad66aSAchin Gupta	ret
97*4f6ad66aSAchin Gupta
98*4f6ad66aSAchin Gupta
99*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
100*4f6ad66aSAchin Gupta	 * void platform_set_stack (int mpidr)
101*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
102*4f6ad66aSAchin Gupta	 */
103*4f6ad66aSAchin Guptaplatform_set_stack:; .type platform_set_stack, %function
104*4f6ad66aSAchin Gupta	mov	x9, x30 // lr
105*4f6ad66aSAchin Gupta	bl	platform_get_core_pos
106*4f6ad66aSAchin Gupta	add	x0, x0, #1
107*4f6ad66aSAchin Gupta	mov	x1, #PLATFORM_STACK_SIZE
108*4f6ad66aSAchin Gupta	mul	x0, x0, x1
109*4f6ad66aSAchin Gupta	ldr	x1, =platform_normal_stacks
110*4f6ad66aSAchin Gupta	add	sp, x1, x0
111*4f6ad66aSAchin Gupta	ret	x9
112*4f6ad66aSAchin Gupta
113*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
114*4f6ad66aSAchin Gupta	 * Placeholder function which should be redefined by
115*4f6ad66aSAchin Gupta	 * each platform.
116*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
117*4f6ad66aSAchin Gupta	 */
118*4f6ad66aSAchin Guptaplatform_check_mpidr:; .type platform_check_mpidr, %function
119*4f6ad66aSAchin Gupta	mov	x0, xzr
120*4f6ad66aSAchin Gupta	ret
121*4f6ad66aSAchin Gupta
122*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
123*4f6ad66aSAchin Gupta	 * Placeholder function which should be redefined by
124*4f6ad66aSAchin Gupta	 * each platform.
125*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
126*4f6ad66aSAchin Gupta	 */
127*4f6ad66aSAchin Guptaplat_report_exception:
128*4f6ad66aSAchin Gupta	ret
129*4f6ad66aSAchin Gupta
130*4f6ad66aSAchin Gupta	/* -----------------------------------------------------
131*4f6ad66aSAchin Gupta	 * Per-cpu stacks in device memory.
132*4f6ad66aSAchin Gupta	 * Used for C code just before power down or right after
133*4f6ad66aSAchin Gupta	 * power up when the MMU or caches need to be turned on
134*4f6ad66aSAchin Gupta	 * or off. Each cpu gets a stack of 512 bytes.
135*4f6ad66aSAchin Gupta	 * -----------------------------------------------------
136*4f6ad66aSAchin Gupta	 */
137*4f6ad66aSAchin Gupta	.section	tzfw_coherent_mem, "aw", %nobits; .align 6
138*4f6ad66aSAchin Gupta
139*4f6ad66aSAchin Guptapcpu_dv_mem_stack:
140*4f6ad66aSAchin Gupta	/* Zero fill */
141*4f6ad66aSAchin Gupta	.space (PLATFORM_CORE_COUNT * PCPU_DV_MEM_STACK_SIZE), 0
142