14f6ad66aSAchin Gupta/* 2e83b0cadSDan Handley * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 44f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 54f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 64f6ad66aSAchin Gupta * 74f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 84f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 94f6ad66aSAchin Gupta * 104f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 114f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 124f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 134f6ad66aSAchin Gupta * 144f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 154f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 164f6ad66aSAchin Gupta * prior written permission. 174f6ad66aSAchin Gupta * 184f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 194f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 204f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 214f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 224f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 234f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 264f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 284f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 294f6ad66aSAchin Gupta */ 304f6ad66aSAchin Gupta 314f6ad66aSAchin Gupta#include <arch.h> 324f6ad66aSAchin Gupta#include <platform.h> 33*0a30cf54SAndrew Thoelke#include <asm_macros.S> 344f6ad66aSAchin Gupta 354f6ad66aSAchin Gupta 364f6ad66aSAchin Gupta .globl pcpu_dv_mem_stack 374f6ad66aSAchin Gupta .weak platform_get_core_pos 384f6ad66aSAchin Gupta .weak platform_set_stack 39c8afc789SAchin Gupta .weak platform_get_stack 404f6ad66aSAchin Gupta .weak platform_is_primary_cpu 414f6ad66aSAchin Gupta .weak platform_set_coherent_stack 424f6ad66aSAchin Gupta .weak platform_check_mpidr 434f6ad66aSAchin Gupta .weak plat_report_exception 444f6ad66aSAchin Gupta 454f6ad66aSAchin Gupta /* ----------------------------------------------------- 46ca823d2cSAchin Gupta * Coherent stack sizes for debug and release builds 474f6ad66aSAchin Gupta * ----------------------------------------------------- 484f6ad66aSAchin Gupta */ 49ca823d2cSAchin Gupta#if DEBUG 50ca823d2cSAchin Gupta#define PCPU_DV_MEM_STACK_SIZE 0x400 51ca823d2cSAchin Gupta#else 52ca823d2cSAchin Gupta#define PCPU_DV_MEM_STACK_SIZE 0x300 53ca823d2cSAchin Gupta#endif 544f6ad66aSAchin Gupta 554f6ad66aSAchin Gupta /* ----------------------------------------------------- 564f6ad66aSAchin Gupta * unsigned long long platform_set_coherent_stack 574f6ad66aSAchin Gupta * (unsigned mpidr); 584f6ad66aSAchin Gupta * For a given mpidr, this function returns the stack 594f6ad66aSAchin Gupta * pointer allocated in device memory. This stack can 604f6ad66aSAchin Gupta * be used by C code which enables/disables the SCTLR.M 614f6ad66aSAchin Gupta * SCTLR.C bit e.g. while powering down a cpu 624f6ad66aSAchin Gupta * ----------------------------------------------------- 634f6ad66aSAchin Gupta */ 64*0a30cf54SAndrew Thoelkefunc platform_set_coherent_stack 654f6ad66aSAchin Gupta mov x5, x30 // lr 664f6ad66aSAchin Gupta bl platform_get_core_pos 674f6ad66aSAchin Gupta add x0, x0, #1 684f6ad66aSAchin Gupta mov x1, #PCPU_DV_MEM_STACK_SIZE 694f6ad66aSAchin Gupta mul x0, x0, x1 704f6ad66aSAchin Gupta ldr x1, =pcpu_dv_mem_stack 714f6ad66aSAchin Gupta add sp, x1, x0 724f6ad66aSAchin Gupta ret x5 734f6ad66aSAchin Gupta 744f6ad66aSAchin Gupta 754f6ad66aSAchin Gupta /* ----------------------------------------------------- 764f6ad66aSAchin Gupta * int platform_get_core_pos(int mpidr); 774f6ad66aSAchin Gupta * With this function: CorePos = (ClusterId * 4) + 784f6ad66aSAchin Gupta * CoreId 794f6ad66aSAchin Gupta * ----------------------------------------------------- 804f6ad66aSAchin Gupta */ 81*0a30cf54SAndrew Thoelkefunc platform_get_core_pos 824f6ad66aSAchin Gupta and x1, x0, #MPIDR_CPU_MASK 834f6ad66aSAchin Gupta and x0, x0, #MPIDR_CLUSTER_MASK 844f6ad66aSAchin Gupta add x0, x1, x0, LSR #6 854f6ad66aSAchin Gupta ret 864f6ad66aSAchin Gupta 874f6ad66aSAchin Gupta 884f6ad66aSAchin Gupta /* ----------------------------------------------------- 894f6ad66aSAchin Gupta * void platform_is_primary_cpu (unsigned int mpid); 904f6ad66aSAchin Gupta * 914f6ad66aSAchin Gupta * Given the mpidr say whether this cpu is the primary 924f6ad66aSAchin Gupta * cpu (applicable ony after a cold boot) 934f6ad66aSAchin Gupta * ----------------------------------------------------- 944f6ad66aSAchin Gupta */ 95*0a30cf54SAndrew Thoelkefunc platform_is_primary_cpu 964f6ad66aSAchin Gupta and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 974f6ad66aSAchin Gupta cmp x0, #PRIMARY_CPU 984f6ad66aSAchin Gupta cset x0, eq 994f6ad66aSAchin Gupta ret 1004f6ad66aSAchin Gupta 1014f6ad66aSAchin Gupta /* ----------------------------------------------------- 102c8afc789SAchin Gupta * void platform_get_stack (unsigned long mpidr) 1034f6ad66aSAchin Gupta * ----------------------------------------------------- 1044f6ad66aSAchin Gupta */ 105*0a30cf54SAndrew Thoelkefunc platform_get_stack 106c8afc789SAchin Gupta mov x10, x30 // lr 1074f6ad66aSAchin Gupta bl platform_get_core_pos 1084f6ad66aSAchin Gupta add x0, x0, #1 1094f6ad66aSAchin Gupta mov x1, #PLATFORM_STACK_SIZE 1104f6ad66aSAchin Gupta mul x0, x0, x1 1114f6ad66aSAchin Gupta ldr x1, =platform_normal_stacks 112c8afc789SAchin Gupta add x0, x1, x0 113c8afc789SAchin Gupta ret x10 114c8afc789SAchin Gupta 115c8afc789SAchin Gupta /* ----------------------------------------------------- 116c8afc789SAchin Gupta * void platform_set_stack (unsigned long mpidr) 117c8afc789SAchin Gupta * ----------------------------------------------------- 118c8afc789SAchin Gupta */ 119*0a30cf54SAndrew Thoelkefunc platform_set_stack 120c8afc789SAchin Gupta mov x9, x30 // lr 121c8afc789SAchin Gupta bl platform_get_stack 122c8afc789SAchin Gupta mov sp, x0 1234f6ad66aSAchin Gupta ret x9 1244f6ad66aSAchin Gupta 1254f6ad66aSAchin Gupta /* ----------------------------------------------------- 1264f6ad66aSAchin Gupta * Placeholder function which should be redefined by 1274f6ad66aSAchin Gupta * each platform. 1284f6ad66aSAchin Gupta * ----------------------------------------------------- 1294f6ad66aSAchin Gupta */ 130*0a30cf54SAndrew Thoelkefunc platform_check_mpidr 1314f6ad66aSAchin Gupta mov x0, xzr 1324f6ad66aSAchin Gupta ret 1334f6ad66aSAchin Gupta 1344f6ad66aSAchin Gupta /* ----------------------------------------------------- 1354f6ad66aSAchin Gupta * Placeholder function which should be redefined by 1364f6ad66aSAchin Gupta * each platform. 1374f6ad66aSAchin Gupta * ----------------------------------------------------- 1384f6ad66aSAchin Gupta */ 139*0a30cf54SAndrew Thoelkefunc plat_report_exception 1404f6ad66aSAchin Gupta ret 1414f6ad66aSAchin Gupta 1424f6ad66aSAchin Gupta /* ----------------------------------------------------- 1434f6ad66aSAchin Gupta * Per-cpu stacks in device memory. 1444f6ad66aSAchin Gupta * Used for C code just before power down or right after 1454f6ad66aSAchin Gupta * power up when the MMU or caches need to be turned on 1464f6ad66aSAchin Gupta * or off. Each cpu gets a stack of 512 bytes. 1474f6ad66aSAchin Gupta * ----------------------------------------------------- 1484f6ad66aSAchin Gupta */ 1494f6ad66aSAchin Gupta .section tzfw_coherent_mem, "aw", %nobits; .align 6 1504f6ad66aSAchin Gupta 1514f6ad66aSAchin Guptapcpu_dv_mem_stack: 1524f6ad66aSAchin Gupta /* Zero fill */ 1534f6ad66aSAchin Gupta .space (PLATFORM_CORE_COUNT * PCPU_DV_MEM_STACK_SIZE), 0 154