1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33 34 .weak plat_my_core_pos 35 .weak plat_reset_handler 36 .weak plat_disable_acp 37 .weak platform_mem_init 38 .weak plat_panic_handler 39 40 /* ----------------------------------------------------- 41 * int plat_my_core_pos(void); 42 * With this function: CorePos = (ClusterId * 4) + 43 * CoreId 44 * ----------------------------------------------------- 45 */ 46func plat_my_core_pos 47 ldcopr r0, MPIDR 48 and r1, r0, #MPIDR_CPU_MASK 49 and r0, r0, #MPIDR_CLUSTER_MASK 50 add r0, r1, r0, LSR #6 51 bx lr 52endfunc plat_my_core_pos 53 54 /* ----------------------------------------------------- 55 * Placeholder function which should be redefined by 56 * each platform. 57 * ----------------------------------------------------- 58 */ 59func plat_reset_handler 60 bx lr 61endfunc plat_reset_handler 62 63 /* ----------------------------------------------------- 64 * Placeholder function which should be redefined by 65 * each platform. 66 * ----------------------------------------------------- 67 */ 68func plat_disable_acp 69 bx lr 70endfunc plat_disable_acp 71 72 /* --------------------------------------------------------------------- 73 * Placeholder function which should be redefined by 74 * each platform. 75 * --------------------------------------------------------------------- 76 */ 77func platform_mem_init 78 bx lr 79endfunc platform_mem_init 80 81 /* ----------------------------------------------------- 82 * void plat_panic_handler(void) __dead2; 83 * Endless loop by default. 84 * ----------------------------------------------------- 85 */ 86func plat_panic_handler 87 b plat_panic_handler 88endfunc plat_panic_handler 89