1*9a40c0fbSSheetal Tigadoli /* 2*9a40c0fbSSheetal Tigadoli * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3*9a40c0fbSSheetal Tigadoli * 4*9a40c0fbSSheetal Tigadoli * SPDX-License-Identifier: BSD-3-Clause 5*9a40c0fbSSheetal Tigadoli */ 6*9a40c0fbSSheetal Tigadoli 7*9a40c0fbSSheetal Tigadoli #include <arch.h> 8*9a40c0fbSSheetal Tigadoli #include <arch_helpers.h> 9*9a40c0fbSSheetal Tigadoli #include <drivers/arm/ccn.h> 10*9a40c0fbSSheetal Tigadoli 11*9a40c0fbSSheetal Tigadoli #include <platform_def.h> 12*9a40c0fbSSheetal Tigadoli 13*9a40c0fbSSheetal Tigadoli static const unsigned char master_to_rn_id_map[] = { 14*9a40c0fbSSheetal Tigadoli PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP 15*9a40c0fbSSheetal Tigadoli }; 16*9a40c0fbSSheetal Tigadoli 17*9a40c0fbSSheetal Tigadoli static const ccn_desc_t bcm_ccn_desc = { 18*9a40c0fbSSheetal Tigadoli .periphbase = PLAT_BRCM_CCN_BASE, 19*9a40c0fbSSheetal Tigadoli .num_masters = ARRAY_SIZE(master_to_rn_id_map), 20*9a40c0fbSSheetal Tigadoli .master_to_rn_id_map = master_to_rn_id_map 21*9a40c0fbSSheetal Tigadoli }; 22*9a40c0fbSSheetal Tigadoli 23*9a40c0fbSSheetal Tigadoli void plat_brcm_interconnect_init(void) 24*9a40c0fbSSheetal Tigadoli { 25*9a40c0fbSSheetal Tigadoli ccn_init(&bcm_ccn_desc); 26*9a40c0fbSSheetal Tigadoli } 27*9a40c0fbSSheetal Tigadoli 28*9a40c0fbSSheetal Tigadoli void plat_brcm_interconnect_enter_coherency(void) 29*9a40c0fbSSheetal Tigadoli { 30*9a40c0fbSSheetal Tigadoli ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 31*9a40c0fbSSheetal Tigadoli } 32*9a40c0fbSSheetal Tigadoli 33*9a40c0fbSSheetal Tigadoli void plat_brcm_interconnect_exit_coherency(void) 34*9a40c0fbSSheetal Tigadoli { 35*9a40c0fbSSheetal Tigadoli ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 36*9a40c0fbSSheetal Tigadoli } 37