1 /* 2 * Copyright (c) 2015 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/ccn.h> 14 #include <drivers/delay_timer.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/mmio.h> 17 #include <lib/psci/psci.h> 18 #include <lib/spinlock.h> 19 #include <plat/common/platform.h> 20 21 #ifdef USE_PAXC 22 #include <chimp.h> 23 #endif 24 #include <cmn_plat_util.h> 25 #include <ihost_pm.h> 26 #include <plat_brcm.h> 27 #include <platform_def.h> 28 29 static uint64_t plat_sec_entrypoint; 30 31 /******************************************************************************* 32 * SR handler called when a power domain is about to be turned on. The 33 * mpidr determines the CPU to be turned on. 34 ******************************************************************************/ 35 static int brcm_pwr_domain_on(u_register_t mpidr) 36 { 37 int cpuid; 38 39 cpuid = plat_brcm_calc_core_pos(mpidr); 40 INFO("mpidr :%lu, cpuid:%d\n", mpidr, cpuid); 41 42 #ifdef USE_SINGLE_CLUSTER 43 if (cpuid > 1) 44 return PSCI_E_INTERN_FAIL; 45 #endif 46 47 ihost_power_on_cluster(mpidr); 48 49 ihost_power_on_secondary_core(mpidr, plat_sec_entrypoint); 50 51 return PSCI_E_SUCCESS; 52 } 53 54 /******************************************************************************* 55 * SR handler called when a power domain has just been powered on after 56 * being turned off earlier. The target_state encodes the low power state that 57 * each level has woken up from. 58 ******************************************************************************/ 59 static void brcm_pwr_domain_on_finish(const psci_power_state_t *target_state) 60 { 61 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); 62 63 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 64 PLAT_LOCAL_STATE_OFF); 65 66 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == 67 PLAT_LOCAL_STATE_OFF) { 68 INFO("Cluster #%lu entering to snoop/dvm domain\n", cluster_id); 69 ccn_enter_snoop_dvm_domain(1 << cluster_id); 70 } 71 72 /* Enable the gic cpu interface */ 73 plat_brcm_gic_pcpu_init(); 74 75 /* Program the gic per-cpu distributor or re-distributor interface */ 76 plat_brcm_gic_cpuif_enable(); 77 78 INFO("Gic Initialization done for this affinity instance\n"); 79 } 80 81 static void __dead2 brcm_system_reset(void) 82 { 83 uint32_t reset_type = SOFT_SYS_RESET_L1; 84 85 #ifdef USE_PAXC 86 if (bcm_chimp_is_nic_mode()) 87 reset_type = SOFT_RESET_L3; 88 #endif 89 INFO("System rebooting - L%d...\n", reset_type); 90 91 plat_soft_reset(reset_type); 92 93 /* Prevent the function to return due to the attribute */ 94 while (1) 95 ; 96 } 97 98 static int brcm_system_reset2(int is_vendor, int reset_type, 99 u_register_t cookie) 100 { 101 INFO("System rebooting - L%d...\n", reset_type); 102 103 plat_soft_reset(reset_type); 104 105 /* 106 * plat_soft_reset cannot return (it is a __dead function), 107 * but brcm_system_reset2 has to return some value, even in 108 * this case. 109 */ 110 return 0; 111 } 112 113 /******************************************************************************* 114 * Export the platform handlers via plat_brcm_psci_pm_ops. The ARM Standard 115 * platform will take care of registering the handlers with PSCI. 116 ******************************************************************************/ 117 const plat_psci_ops_t plat_brcm_psci_pm_ops = { 118 .pwr_domain_on = brcm_pwr_domain_on, 119 .pwr_domain_on_finish = brcm_pwr_domain_on_finish, 120 .system_reset = brcm_system_reset, 121 .system_reset2 = brcm_system_reset2 122 }; 123 124 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 125 const plat_psci_ops_t **psci_ops) 126 { 127 *psci_ops = &plat_brcm_psci_pm_ops; 128 plat_sec_entrypoint = sec_entrypoint; 129 130 return 0; 131 } 132