1 /* 2 * Copyright (c) 2016 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/delay_timer.h> 9 #include <lib/mmio.h> 10 11 #include <dmu.h> 12 #include <ihost_pm.h> 13 #include <platform_def.h> 14 15 #define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST1 2 16 #define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST2 1 17 #define CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST3 0 18 #define CDRU_MISC_RESET_CONTROL__CDRU_IH1_RESET 9 19 #define CDRU_MISC_RESET_CONTROL__CDRU_IH2_RESET 8 20 #define CDRU_MISC_RESET_CONTROL__CDRU_IH3_RESET 7 21 #define A72_CRM_SOFTRESETN_0 0x480 22 #define A72_CRM_SOFTRESETN_1 0x484 23 #define A72_CRM_DOMAIN_4_CONTROL 0x810 24 #define A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_DFT 3 25 #define A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_MEM 6 26 #define A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_I_O 0 27 #define A72_CRM_SUBSYSTEM_MEMORY_CONTROL_3 0xB4C 28 #define MEMORY_PDA_HI_SHIFT 0x0 29 #define A72_CRM_PLL_PWR_ON 0x70 30 #define A72_CRM_PLL_PWR_ON__PLL0_ISO_PLLOUT 4 31 #define A72_CRM_PLL_PWR_ON__PLL0_PWRON_LDO 1 32 #define A72_CRM_PLL_PWR_ON__PLL0_PWRON_PLL 0 33 #define A72_CRM_SUBSYSTEM_MEMORY_CONTROL_2 0xB48 34 #define A72_CRM_PLL_INTERRUPT_STATUS 0x8c 35 #define A72_CRM_PLL_INTERRUPT_STATUS__PLL0_LOCK_LOST_STATUS 8 36 #define A72_CRM_PLL_INTERRUPT_STATUS__PLL0_LOCK_STATUS 9 37 #define A72_CRM_INTERRUPT_ENABLE 0x4 38 #define A72_CRM_INTERRUPT_ENABLE__PLL0_INT_ENABLE 4 39 #define A72_CRM_PLL_INTERRUPT_ENABLE 0x88 40 #define A72_CRM_PLL_INTERRUPT_ENABLE__PLL0_LOCK_STATUS_INT_ENB 9 41 #define A72_CRM_PLL_INTERRUPT_ENABLE__PLL0_LOCK_LOST_STATUS_INT_ENB 8 42 #define A72_CRM_PLL0_CFG0_CTRL 0x120 43 #define A72_CRM_PLL0_CFG1_CTRL 0x124 44 #define A72_CRM_PLL0_CFG2_CTRL 0x128 45 #define A72_CRM_PLL0_CFG3_CTRL 0x12C 46 #define A72_CRM_CORE_CONFIG_DBGCTRL__DBGROMADDRV 0 47 #define A72_CRM_CORE_CONFIG_DBGCTRL 0xD50 48 #define A72_CRM_CORE_CONFIG_DBGROM_LO 0xD54 49 #define A72_CRM_CORE_CONFIG_DBGROM_HI 0xD58 50 #define A72_CRM_SUBSYSTEM_CONFIG_1__DBGL1RSTDISABLE 2 51 #define A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN 0 52 #define A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN 1 53 #define A72_CRM_AXI_CLK_DESC 0x304 54 #define A72_CRM_ACP_CLK_DESC 0x308 55 #define A72_CRM_ATB_CLK_DESC 0x30C 56 #define A72_CRM_PCLKDBG_DESC 0x310 57 #define A72_CRM_CLOCK_MODE_CONTROL 0x40 58 #define A72_CRM_CLOCK_MODE_CONTROL__CLK_CHANGE_TRIGGER 0 59 #define A72_CRM_CLOCK_CONTROL_0 0x200 60 #define A72_CRM_CLOCK_CONTROL_0__ARM_HW_SW_ENABLE_SEL 0 61 #define A72_CRM_CLOCK_CONTROL_0__AXI_HW_SW_ENABLE_SEL 2 62 #define A72_CRM_CLOCK_CONTROL_0__ACP_HW_SW_ENABLE_SEL 4 63 #define A72_CRM_CLOCK_CONTROL_0__ATB_HW_SW_ENABLE_SEL 6 64 #define A72_CRM_CLOCK_CONTROL_0__PCLKDBG_HW_SW_ENA_SEL 8 65 #define A72_CRM_CLOCK_CONTROL_1 0x204 66 #define A72_CRM_CLOCK_CONTROL_1__TMON_HW_SW_ENABLE_SEL 6 67 #define A72_CRM_CLOCK_CONTROL_1__APB_HW_SW_ENABLE_SEL 8 68 #define A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN 0 69 #define A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN 1 70 #define A72_CRM_SOFTRESETN_0__AXI_SOFTRESETN 9 71 #define A72_CRM_SOFTRESETN_0__ACP_SOFTRESETN 10 72 #define A72_CRM_SOFTRESETN_0__ATB_SOFTRESETN 11 73 #define A72_CRM_SOFTRESETN_0__PCLKDBG_SOFTRESETN 12 74 #define A72_CRM_SOFTRESETN_0__TMON_SOFTRESETN 15 75 #define A72_CRM_SOFTRESETN_0__L2_SOFTRESETN 3 76 #define A72_CRM_SOFTRESETN_1__APB_SOFTRESETN 8 77 78 /* core related regs */ 79 #define A72_CRM_DOMAIN_0_CONTROL 0x800 80 #define A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_MEM 0x6 81 #define A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_I_O 0x0 82 #define A72_CRM_DOMAIN_1_CONTROL 0x804 83 #define A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_MEM 0x6 84 #define A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_I_O 0x0 85 #define A72_CRM_CORE_CONFIG_RVBA0_LO 0xD10 86 #define A72_CRM_CORE_CONFIG_RVBA0_MID 0xD14 87 #define A72_CRM_CORE_CONFIG_RVBA0_HI 0xD18 88 #define A72_CRM_CORE_CONFIG_RVBA1_LO 0xD20 89 #define A72_CRM_CORE_CONFIG_RVBA1_MID 0xD24 90 #define A72_CRM_CORE_CONFIG_RVBA1_HI 0xD28 91 #define A72_CRM_SUBSYSTEM_CONFIG_0 0xC80 92 #define A72_CRM_SUBSYSTEM_CONFIG_0__DBGPWRDUP_CFG_SHIFT 4 93 #define A72_CRM_SOFTRESETN_0__COREPOR0_SOFTRESETN 4 94 #define A72_CRM_SOFTRESETN_0__COREPOR1_SOFTRESETN 5 95 #define A72_CRM_SOFTRESETN_1__CORE0_SOFTRESETN 0 96 #define A72_CRM_SOFTRESETN_1__DEBUG0_SOFTRESETN 4 97 #define A72_CRM_SOFTRESETN_1__CORE1_SOFTRESETN 1 98 #define A72_CRM_SOFTRESETN_1__DEBUG1_SOFTRESETN 5 99 100 #define SPROC_MEMORY_BISR 0 101 102 static int cluster_power_status[PLAT_BRCM_CLUSTER_COUNT] = {CLUSTER_POWER_ON, 103 CLUSTER_POWER_OFF, 104 CLUSTER_POWER_OFF, 105 CLUSTER_POWER_OFF}; 106 107 void ihost_power_on_cluster(u_register_t mpidr) 108 { 109 uint32_t rst, d2xs; 110 uint32_t cluster_id; 111 uint32_t ihost_base; 112 #if SPROC_MEMORY_BISR 113 uint32_t bisr, cnt; 114 #endif 115 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 116 uint32_t cluster0_freq_sel; 117 118 if (cluster_power_status[cluster_id] == CLUSTER_POWER_ON) 119 return; 120 121 cluster_power_status[cluster_id] = CLUSTER_POWER_ON; 122 INFO("enabling Cluster #%u\n", cluster_id); 123 124 switch (cluster_id) { 125 case 1: 126 rst = (1 << CDRU_MISC_RESET_CONTROL__CDRU_IH1_RESET); 127 d2xs = (1 << CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST1); 128 #if SPROC_MEMORY_BISR 129 bisr = CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST1; 130 #endif 131 break; 132 case 2: 133 rst = (1 << CDRU_MISC_RESET_CONTROL__CDRU_IH2_RESET); 134 d2xs = (1 << CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST2); 135 #if SPROC_MEMORY_BISR 136 bisr = CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST2; 137 #endif 138 break; 139 case 3: 140 rst = (1 << CDRU_MISC_RESET_CONTROL__CDRU_IH3_RESET); 141 d2xs = (1 << CDRU_CCN_REGISTER_CONTROL_1__D2XS_PD_IHOST3); 142 #if SPROC_MEMORY_BISR 143 bisr = CRMU_BISR_PDG_MASK__CRMU_BISR_IHOST3; 144 #endif 145 break; 146 default: 147 ERROR("Invalid cluster :%u\n", cluster_id); 148 return; 149 } 150 151 /* Releasing ihost resets */ 152 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, rst); 153 154 /* calculate cluster/ihost base address */ 155 ihost_base = IHOST0_BASE + cluster_id * IHOST_ADDR_SPACE; 156 157 /* Remove Cluster IO isolation */ 158 mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_4_CONTROL, 159 (1 << A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_I_O), 160 (1 << A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_DFT) | 161 (1 << A72_CRM_DOMAIN_4_CONTROL__DOMAIN_4_ISO_MEM)); 162 163 /* 164 * Since BISR sequence requires that all cores of cluster should 165 * have removed I/O isolation hence doing same here. 166 */ 167 /* Remove core0 memory IO isolations */ 168 mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_0_CONTROL, 169 (1 << A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_I_O), 170 (1 << A72_CRM_DOMAIN_0_CONTROL__DOMAIN_0_ISO_MEM)); 171 172 /* Remove core1 memory IO isolations */ 173 mmio_clrsetbits_32(ihost_base + A72_CRM_DOMAIN_1_CONTROL, 174 (1 << A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_I_O), 175 (1 << A72_CRM_DOMAIN_1_CONTROL__DOMAIN_1_ISO_MEM)); 176 177 #if SPROC_MEMORY_BISR 178 mmio_setbits_32(CRMU_BISR_PDG_MASK, (1 << bisr)); 179 180 if (!(mmio_read_32(CDRU_CHIP_STRAP_DATA_LSW) & 181 (1 << CDRU_CHIP_STRAP_DATA_LSW__BISR_BYPASS_MODE))) { 182 /* BISR completion would take max 2 usec */ 183 cnt = 0; 184 while (cnt < 2) { 185 udelay(1); 186 if (mmio_read_32(CRMU_CHIP_OTPC_STATUS) & 187 (1 << CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE)) 188 break; 189 cnt++; 190 } 191 } 192 193 /* if BISR is not completed, need to be checked with ASIC team */ 194 if (((mmio_read_32(CRMU_CHIP_OTPC_STATUS)) & 195 (1 << CRMU_CHIP_OTPC_STATUS__OTP_BISR_LOAD_DONE)) == 0) { 196 WARN("BISR did not completed and need to be addressed\n"); 197 } 198 #endif 199 200 /* PLL Power up. supply is already on. Turn on PLL LDO/PWR */ 201 mmio_write_32(ihost_base + A72_CRM_PLL_PWR_ON, 202 (1 << A72_CRM_PLL_PWR_ON__PLL0_ISO_PLLOUT) | 203 (1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_LDO) | 204 (1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_PLL)); 205 206 /* 1us in spec; Doubling it to be safe*/ 207 udelay(2); 208 209 /* Remove PLL output ISO */ 210 mmio_write_32(ihost_base + A72_CRM_PLL_PWR_ON, 211 (1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_LDO) | 212 (1 << A72_CRM_PLL_PWR_ON__PLL0_PWRON_PLL)); 213 214 /* 215 * PLL0 Configuration Control Register 216 * these 4 registers drive the i_pll_ctrl[63:0] input of pll 217 * (16b per register). 218 * the values are derived from the spec (sections 8 and 10). 219 */ 220 221 mmio_write_32(ihost_base + A72_CRM_PLL0_CFG0_CTRL, 0x00000000); 222 mmio_write_32(ihost_base + A72_CRM_PLL0_CFG1_CTRL, 0x00008400); 223 mmio_write_32(ihost_base + A72_CRM_PLL0_CFG2_CTRL, 0x00000001); 224 mmio_write_32(ihost_base + A72_CRM_PLL0_CFG3_CTRL, 0x00000000); 225 226 /* Read the freq_sel from cluster 0, which is up already */ 227 cluster0_freq_sel = bcm_get_ihost_pll_freq(0); 228 bcm_set_ihost_pll_freq(cluster_id, cluster0_freq_sel); 229 230 udelay(1); 231 232 /* Release clock source reset */ 233 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, 234 (1 << A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN) | 235 (1 << A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN)); 236 237 udelay(1); 238 239 /* 240 * Integer division for clks (divider value = n+1). 241 * These are the divisor of ARM PLL clock frequecy. 242 */ 243 mmio_write_32(ihost_base + A72_CRM_AXI_CLK_DESC, 0x00000001); 244 mmio_write_32(ihost_base + A72_CRM_ACP_CLK_DESC, 0x00000001); 245 mmio_write_32(ihost_base + A72_CRM_ATB_CLK_DESC, 0x00000004); 246 mmio_write_32(ihost_base + A72_CRM_PCLKDBG_DESC, 0x0000000b); 247 248 /* 249 * clock change trigger - must set to take effect after clock 250 * source change 251 */ 252 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_MODE_CONTROL, 253 (1 << A72_CRM_CLOCK_MODE_CONTROL__CLK_CHANGE_TRIGGER)); 254 255 /* turn on functional clocks */ 256 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_0, 257 (3 << A72_CRM_CLOCK_CONTROL_0__ARM_HW_SW_ENABLE_SEL) | 258 (3 << A72_CRM_CLOCK_CONTROL_0__AXI_HW_SW_ENABLE_SEL) | 259 (3 << A72_CRM_CLOCK_CONTROL_0__ACP_HW_SW_ENABLE_SEL) | 260 (3 << A72_CRM_CLOCK_CONTROL_0__ATB_HW_SW_ENABLE_SEL) | 261 (3 << A72_CRM_CLOCK_CONTROL_0__PCLKDBG_HW_SW_ENA_SEL)); 262 263 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_1, 264 (3 << A72_CRM_CLOCK_CONTROL_1__TMON_HW_SW_ENABLE_SEL) | 265 (3 << A72_CRM_CLOCK_CONTROL_1__APB_HW_SW_ENABLE_SEL)); 266 267 /* Program D2XS Power Down Registers */ 268 mmio_setbits_32(CDRU_CCN_REGISTER_CONTROL_1, d2xs); 269 270 /* Program Core Config Debug ROM Address Registers */ 271 /* mark valid for Debug ROM base address */ 272 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_DBGCTRL, 273 (1 << A72_CRM_CORE_CONFIG_DBGCTRL__DBGROMADDRV)); 274 275 /* Program Lo and HI address of coresight DBG rom address */ 276 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_DBGROM_LO, 277 (CORESIGHT_BASE_ADDR >> 12) & 0xffff); 278 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_DBGROM_HI, 279 (CORESIGHT_BASE_ADDR >> 28) & 0xffff); 280 281 /* 282 * Release soft resets of different components. 283 * Order: Bus clocks --> PERIPH --> L2 --> cores 284 */ 285 286 /* Bus clocks soft resets */ 287 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, 288 (1 << A72_CRM_SOFTRESETN_0__CRYSTAL26_SOFTRESETN) | 289 (1 << A72_CRM_SOFTRESETN_0__CRM_PLL0_SOFTRESETN) | 290 (1 << A72_CRM_SOFTRESETN_0__AXI_SOFTRESETN) | 291 (1 << A72_CRM_SOFTRESETN_0__ACP_SOFTRESETN) | 292 (1 << A72_CRM_SOFTRESETN_0__ATB_SOFTRESETN) | 293 (1 << A72_CRM_SOFTRESETN_0__PCLKDBG_SOFTRESETN)); 294 295 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1, 296 (1 << A72_CRM_SOFTRESETN_1__APB_SOFTRESETN)); 297 298 /* Periph component softreset */ 299 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, 300 (1 << A72_CRM_SOFTRESETN_0__TMON_SOFTRESETN)); 301 302 /* L2 softreset */ 303 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, 304 (1 << A72_CRM_SOFTRESETN_0__L2_SOFTRESETN)); 305 306 /* Enable and program Satellite timer */ 307 ihost_enable_satellite_timer(cluster_id); 308 } 309 310 void ihost_power_on_secondary_core(u_register_t mpidr, uint64_t rvbar) 311 { 312 uint32_t ihost_base; 313 uint32_t coreid = MPIDR_AFFLVL0_VAL(mpidr); 314 uint32_t cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 315 316 ihost_base = IHOST0_BASE + cluster_id * IHOST_ADDR_SPACE; 317 INFO("programming core #%u\n", coreid); 318 319 if (coreid) { 320 /* program the entry point for core1 */ 321 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA1_LO, 322 rvbar & 0xFFFF); 323 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA1_MID, 324 (rvbar >> 16) & 0xFFFF); 325 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA1_HI, 326 (rvbar >> 32) & 0xFFFF); 327 } else { 328 /* program the entry point for core */ 329 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA0_LO, 330 rvbar & 0xFFFF); 331 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA0_MID, 332 (rvbar >> 16) & 0xFFFF); 333 mmio_write_32(ihost_base + A72_CRM_CORE_CONFIG_RVBA0_HI, 334 (rvbar >> 32) & 0xFFFF); 335 } 336 337 /* Tell debug logic which processor is up */ 338 mmio_setbits_32(ihost_base + A72_CRM_SUBSYSTEM_CONFIG_0, 339 (coreid ? 340 (2 << A72_CRM_SUBSYSTEM_CONFIG_0__DBGPWRDUP_CFG_SHIFT) : 341 (1 << A72_CRM_SUBSYSTEM_CONFIG_0__DBGPWRDUP_CFG_SHIFT))); 342 343 /* releasing soft resets for IHOST core */ 344 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, 345 (coreid ? 346 (1 << A72_CRM_SOFTRESETN_0__COREPOR1_SOFTRESETN) : 347 (1 << A72_CRM_SOFTRESETN_0__COREPOR0_SOFTRESETN))); 348 349 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1, 350 (coreid ? 351 ((1 << A72_CRM_SOFTRESETN_1__CORE1_SOFTRESETN) | 352 (1 << A72_CRM_SOFTRESETN_1__DEBUG1_SOFTRESETN)) : 353 ((1 << A72_CRM_SOFTRESETN_1__CORE0_SOFTRESETN) | 354 (1 << A72_CRM_SOFTRESETN_1__DEBUG0_SOFTRESETN)))); 355 } 356