1 /* 2 * Copyright (c) 2016-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/bl_common.h> 9 #include <common/debug.h> 10 #include <drivers/arm/sp805.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 14 #include <chimp.h> 15 #include <chip_id.h> 16 #include <cmn_plat_util.h> 17 #include <dmu.h> 18 #include <fru.h> 19 #ifdef USE_GPIO 20 #include <drivers/gpio.h> 21 #include <iproc_gpio.h> 22 #endif 23 #include <platform_def.h> 24 #include <sotp.h> 25 #include <swreg.h> 26 #include <sr_utils.h> 27 #ifdef USE_DDR 28 #include <ddr_init.h> 29 #else 30 #include <ext_sram_init.h> 31 #endif 32 #if DRIVER_OCOTP_ENABLE 33 #include <ocotp.h> 34 #endif 35 #include "board_info.h" 36 37 #define WORD_SIZE 8 38 #define SWREG_AVS_OTP_OFFSET (13 * WORD_SIZE) /* 13th row byte offset */ 39 #define AON_GPIO_OTP_OFFSET (28 * WORD_SIZE) /* 28th row byte offset */ 40 #define BYTES_TO_READ 8 41 42 /* OTP voltage step definitions */ 43 #define MVOLT_STEP_MAX 0x18 /* 1v */ 44 #define MVOLT_PER_STEP 10 /* 0.01mv per step */ 45 #define MVOLT_BASE 760 /* 0.76v */ 46 47 #define STEP_TO_UVOLTS(step) \ 48 ((MVOLT_BASE + (MVOLT_PER_STEP * (step))) * 1000) 49 50 #define GET_BITS(first, last, data) \ 51 ((data >> first) & ((1 << (last - first + 1)) - 1)) 52 53 /* 54 * SW-REG OTP encoding: 55 * 56 * SWREG_bits[11:0] = OTP 13th row 12 bits[55:44] 57 * SWREG_bits[11:10] - Valid Bits (0x2 - valid, if not 0x2 - Invalid) 58 * SWREG_bits[9:5] - iHost03, iHost12 59 * SWREG_bits[4:0] - Core VDDC 60 */ 61 #define SWREG_OTP_BITS_START 12 /* 44th bit in MSB 32-bits */ 62 #define SWREG_OTP_BITS_END 23 /* 55th bit in MSB 32-bits */ 63 #define SWREG_VDDC_FIELD_START 0 64 #define SWREG_VDDC_FIELD_END 4 65 #define SWREG_IHOST_FIELD_START 5 66 #define SWREG_IHOST_FIELD_END 9 67 #define SWREG_VALID_BIT_START 10 68 #define SWREG_VALID_BIT_END 11 69 #define SWREG_VALID_BITS 0x2 70 71 /* 72 * Row 13 bit 56 is programmed as '1' today. It is not being used, so plan 73 * is to flip this bit to '0' for B1 rev. Hence SW can leverage this bit 74 * to identify Bx chip to program different sw-regulators. 75 */ 76 #define SPARE_BIT 24 77 78 #define IS_SR_B0(data) (((data) >> SPARE_BIT) & 0x1) 79 80 #if DRIVER_OCOTP_ENABLE 81 static struct otpc_map otp_stingray_map = { 82 .otpc_row_size = 2, 83 .data_r_offset = {0x10, 0x5c}, 84 .data_w_offset = {0x2c, 0x64}, 85 .word_size = 8, 86 .stride = 8, 87 }; 88 #endif 89 90 void plat_bcm_bl2_early_platform_setup(void) 91 { 92 /* Select UART0 for AP via mux setting*/ 93 if (PLAT_BRCM_BOOT_UART_BASE == UART0_BASE_ADDR) { 94 mmio_write_32(UART0_SIN_MODE_SEL_CONTROL, 1); 95 mmio_write_32(UART0_SOUT_MODE_SEL_CONTROL, 1); 96 } 97 } 98 99 #ifdef USE_NAND 100 static void brcm_stingray_nand_init(void) 101 { 102 unsigned int val; 103 unsigned int nand_idm_reset_control = 0x68e0a800; 104 105 VERBOSE(" stingray nand init start.\n"); 106 107 /* Reset NAND */ 108 VERBOSE(" - reset nand\n"); 109 val = mmio_read_32((uintptr_t)(nand_idm_reset_control + 0x0)); 110 mmio_write_32((uintptr_t)(nand_idm_reset_control + 0x0), val | 0x1); 111 udelay(500); 112 val = mmio_read_32((uintptr_t)(nand_idm_reset_control + 0x0)); 113 mmio_write_32((uintptr_t)(nand_idm_reset_control + 0x0), val & ~0x1); 114 udelay(500); 115 116 VERBOSE(" stingray nand init done.\n"); 117 } 118 #endif 119 120 #if defined(USE_PAXB) || defined(USE_PAXC) || defined(USE_SATA) 121 #define PCIE_RESCAL_CFG_0 0x40000130 122 #define PCIE_CFG_RESCAL_RSTB_R (1 << 16) 123 #define PCIE_CFG_RESCAL_PWRDNB_R (1 << 8) 124 #define PCIE_RESCAL_STATUS_0 0x4000014c 125 #define PCIE_STAT_PON_VALID_R (1 << 0) 126 #define PCIE_RESCAL_OUTPUT_STATUS 0x40000154 127 #define CDRU_PCIE_RESET_N_R (1 << CDRU_MISC_RESET_CONTROL__CDRU_PCIE_RESET_N_R) 128 129 #ifdef EMULATION_SETUP 130 static void brcm_stingray_pcie_reset(void) 131 { 132 } 133 #else 134 static void brcm_stingray_pcie_reset(void) 135 { 136 unsigned int data; 137 int try; 138 139 if (bcm_chimp_is_nic_mode()) { 140 INFO("NIC mode detected; PCIe reset/rescal not executed\n"); 141 return; 142 } 143 144 mmio_clrbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PCIE_RESET_N_R); 145 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PCIE_RESET_N_R); 146 /* Release reset */ 147 mmio_setbits_32(PCIE_RESCAL_CFG_0, PCIE_CFG_RESCAL_RSTB_R); 148 mdelay(1); 149 /* Power UP */ 150 mmio_setbits_32(PCIE_RESCAL_CFG_0, 151 (PCIE_CFG_RESCAL_RSTB_R | PCIE_CFG_RESCAL_PWRDNB_R)); 152 153 try = 1000; 154 do { 155 udelay(1); 156 data = mmio_read_32(PCIE_RESCAL_STATUS_0); 157 try--; 158 } while ((data & PCIE_STAT_PON_VALID_R) == 0x0 && (try > 0)); 159 160 if (try <= 0) 161 ERROR("PCIE_RESCAL_STATUS_0: 0x%x\n", data); 162 163 VERBOSE("PCIE_SATA_RESCAL_STATUS_0 0x%x.\n", 164 mmio_read_32(PCIE_RESCAL_STATUS_0)); 165 VERBOSE("PCIE_SATA_RESCAL_OUTPUT_STATUS 0x%x.\n", 166 mmio_read_32(PCIE_RESCAL_OUTPUT_STATUS)); 167 INFO("PCIE SATA Rescal Init done\n"); 168 } 169 #endif /* EMULATION_SETUP */ 170 #endif /* USE_PAXB || USE_PAXC || USE_SATA */ 171 172 #ifdef USE_PAXC 173 void brcm_stingray_chimp_check_and_fastboot(void) 174 { 175 int fastboot_init_result; 176 177 if (bcm_chimp_is_nic_mode()) 178 /* Do not wait here */ 179 return; 180 181 #if WARMBOOT_DDR_S3_SUPPORT 182 /* 183 * Currently DDR shmoo parameters and QSPI boot source are 184 * tied. DDR shmoo parameters are stored in QSPI, which is 185 * used for warmboot. 186 * Do not reset nitro for warmboot 187 */ 188 if (is_warmboot() && (boot_source_get() == BOOT_SOURCE_QSPI)) 189 return; 190 #endif /* WARMBOOT_DDR_S3_SUPPORT */ 191 192 /* 193 * Not in NIC mode, 194 * initiate fastboot (if enabled) 195 */ 196 if (FASTBOOT_TYPE == CHIMP_FASTBOOT_NITRO_RESET) { 197 198 VERBOSE("Bring up Nitro/ChiMP\n"); 199 200 if (boot_source_get() == BOOT_SOURCE_QSPI) 201 WARN("Nitro boots from QSPI when AP has booted from QSPI.\n"); 202 brcm_stingray_set_qspi_mux(0); 203 VERBOSE("Nitro controls the QSPI\n"); 204 } 205 206 fastboot_init_result = bcm_chimp_initiate_fastboot(FASTBOOT_TYPE); 207 if (fastboot_init_result && boot_source_get() != BOOT_SOURCE_QSPI) 208 ERROR("Nitro init error %d. Status: 0x%x; bpe_mod reg: 0x%x\n" 209 "fastboot register: 0x%x; handshake register 0x%x\n", 210 fastboot_init_result, 211 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_STAT_REG), 212 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_MODE_REG), 213 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_FSTBOOT_PTR_REG), 214 bcm_chimp_read(CHIMP_REG_ECO_RESERVED)); 215 216 /* 217 * CRMU watchdog kicks is an example, which is L1 reset, 218 * does not clear Nitro scratch pad ram. 219 * For Nitro resets: Clear the Nitro health status memory. 220 */ 221 bcm_chimp_write((CHIMP_REG_CHIMP_SCPAD + CHIMP_HEALTH_STATUS_OFFSET), 222 0); 223 } 224 #endif 225 226 void set_ihost_vddc_swreg(uint32_t ihost_uvolts, uint32_t vddc_uvolts) 227 { 228 NOTICE("ihost_uvolts: %duv, vddc_uvolts: %duv\n", 229 ihost_uvolts, vddc_uvolts); 230 231 set_swreg(VDDC_CORE, vddc_uvolts); 232 set_swreg(IHOST03, ihost_uvolts); 233 set_swreg(IHOST12, ihost_uvolts); 234 } 235 236 /* 237 * Reads SWREG AVS OTP bits (13th row) with ECC enabled and get voltage 238 * defined in OTP if valid OTP is found 239 */ 240 void read_avs_otp_bits(uint32_t *ihost_uvolts, uint32_t *vddc_uvolts) 241 { 242 uint32_t offset = SWREG_AVS_OTP_OFFSET; 243 uint32_t ihost_step, vddc_step; 244 uint32_t avs_bits; 245 uint32_t buf[2]; 246 247 if (bcm_otpc_read(offset, &buf[0], BYTES_TO_READ, 1) == -1) 248 return; 249 250 VERBOSE("AVS OTP %d ROW: 0x%x.0x%x\n", 251 offset/WORD_SIZE, buf[1], buf[0]); 252 253 /* get voltage readings from AVS OTP bits */ 254 avs_bits = GET_BITS(SWREG_OTP_BITS_START, 255 SWREG_OTP_BITS_END, 256 buf[1]); 257 258 /* check for valid otp bits */ 259 if (GET_BITS(SWREG_VALID_BIT_START, SWREG_VALID_BIT_END, avs_bits) != 260 SWREG_VALID_BITS) { 261 WARN("Invalid AVS OTP bits at %d row\n", offset/WORD_SIZE); 262 return; 263 } 264 265 /* get ihost and vddc step value */ 266 vddc_step = GET_BITS(SWREG_VDDC_FIELD_START, 267 SWREG_VDDC_FIELD_END, 268 avs_bits); 269 270 ihost_step = GET_BITS(SWREG_IHOST_FIELD_START, 271 SWREG_IHOST_FIELD_END, 272 avs_bits); 273 274 if ((ihost_step > MVOLT_STEP_MAX) || (vddc_step > MVOLT_STEP_MAX)) { 275 WARN("OTP entry invalid\n"); 276 return; 277 } 278 279 /* get voltage in micro-volts */ 280 *ihost_uvolts = STEP_TO_UVOLTS(ihost_step); 281 *vddc_uvolts = STEP_TO_UVOLTS(vddc_step); 282 } 283 284 /* 285 * This api reads otp bits and program internal swreg's - ihos12, ihost03, 286 * vddc_core and ddr_core based on different chip. External swreg's 287 * programming will be done from crmu. 288 * 289 * For A2 chip: 290 * Read OTP row 20, bit 50. This bit will be set for A2 chip. Once A2 chip is 291 * found, read AVS OTP row 13, 12bits[55:44], if valid otp bits are found 292 * then set ihost and vddc according to avs otp bits else set them to 0.94v 293 * and 0.91v respectively. Also update the firmware after setting voltage. 294 * 295 * For B0 chip: 296 * Read OTP row 13, bit 56. This bit will be set for B0 chip. Once B0 chip is 297 * found then set ihost and vddc to 0.95v and ddr_core to 1v. No AVS OTP bits 298 * are used get ihost/vddc voltages. 299 * 300 * For B1 chip: 301 * Read AVS OTP row 13, 12bits[55:44], if valid otp bits are found then set 302 * ihost and vddc according to avs otp bits else set them to 0.94v and 0.91v 303 * respectively. 304 */ 305 void set_swreg_based_on_otp(void) 306 { 307 /* default voltage if no valid OTP */ 308 uint32_t vddc_uvolts = VDDC_CORE_DEF_VOLT; 309 uint32_t ihost_uvolts = IHOST_DEF_VOLT; 310 uint32_t ddrc_uvolts; 311 uint32_t offset; 312 uint32_t buf[2]; 313 314 offset = SWREG_AVS_OTP_OFFSET; 315 if (bcm_otpc_read(offset, &buf[0], BYTES_TO_READ, 1) == -1) 316 return; 317 318 VERBOSE("OTP %d ROW: 0x%x.0x%x\n", 319 offset/WORD_SIZE, buf[1], buf[0]); 320 321 if (IS_SR_B0(buf[1])) { 322 /* don't read AVS OTP for B0 */ 323 ihost_uvolts = B0_IHOST_DEF_VOLT; 324 vddc_uvolts = B0_VDDC_CORE_DEF_VOLT; 325 ddrc_uvolts = B0_DDR_VDDC_DEF_VOLT; 326 } else { 327 read_avs_otp_bits(&ihost_uvolts, &vddc_uvolts); 328 } 329 330 #if (IHOST_REG_TYPE == IHOST_REG_INTEGRATED) && \ 331 (VDDC_REG_TYPE == VDDC_REG_INTEGRATED) 332 /* enable IHOST12 cluster before changing voltage */ 333 NOTICE("Switching on the Regulator idx: %u\n", 334 SWREG_IHOST1_DIS); 335 mmio_clrsetbits_32(CRMU_SWREG_CTRL_ADDR, 336 BIT(SWREG_IHOST1_DIS), 337 BIT(SWREG_IHOST1_REG_RESETB)); 338 339 /* wait for regulator supply gets stable */ 340 while (!(mmio_read_32(CRMU_SWREG_STATUS_ADDR) & 341 (1 << SWREG_IHOST1_PMU_STABLE))) 342 ; 343 344 INFO("Regulator supply got stable\n"); 345 346 #ifndef DEFAULT_SWREG_CONFIG 347 swreg_firmware_update(); 348 #endif 349 350 set_ihost_vddc_swreg(ihost_uvolts, vddc_uvolts); 351 #endif 352 if (IS_SR_B0(buf[1])) { 353 NOTICE("ddrc_uvolts: %duv\n", ddrc_uvolts); 354 set_swreg(DDR_VDDC, ddrc_uvolts); 355 } 356 } 357 358 #ifdef USE_DDR 359 static struct ddr_info ddr_info; 360 #endif 361 #ifdef USE_FRU 362 static struct fru_area_info fru_area[FRU_MAX_NR_AREAS]; 363 static struct fru_board_info board_info; 364 static struct fru_time fru_tm; 365 static uint8_t fru_tbl[BCM_MAX_FRU_LEN]; 366 367 static void board_detect_fru(void) 368 { 369 uint32_t i, result; 370 int ret = -1; 371 372 result = bcm_emmc_init(false); 373 if (!result) { 374 ERROR("eMMC init failed\n"); 375 return; 376 } 377 378 /* go through eMMC boot partitions looking for FRU table */ 379 for (i = EMMC_BOOT_PARTITION1; i <= EMMC_BOOT_PARTITION2; i++) { 380 result = emmc_partition_select(i); 381 if (!result) { 382 ERROR("Switching to eMMC part %u failed\n", i); 383 return; 384 } 385 386 result = emmc_read(BCM_FRU_TBL_OFFSET, (uintptr_t)fru_tbl, 387 BCM_MAX_FRU_LEN, BCM_MAX_FRU_LEN); 388 if (!result) { 389 ERROR("Failed to read from eMMC part %u\n", i); 390 return; 391 } 392 393 /* 394 * Run sanity check and checksum to make sure valid FRU table 395 * is detected 396 */ 397 ret = fru_validate(fru_tbl, fru_area); 398 if (ret < 0) { 399 WARN("FRU table not found in eMMC part %u\n", i); 400 continue; 401 } 402 403 /* parse DDR information from FRU table */ 404 ret = fru_parse_ddr(fru_tbl, &fru_area[FRU_AREA_INTERNAL], 405 &ddr_info); 406 if (ret < 0) { 407 WARN("No FRU DDR info found in eMMC part %u\n", i); 408 continue; 409 } 410 411 /* parse board information from FRU table */ 412 ret = fru_parse_board(fru_tbl, &fru_area[FRU_AREA_BOARD_INFO], 413 &board_info); 414 if (ret < 0) { 415 WARN("No FRU board info found in eMMC part %u\n", i); 416 continue; 417 } 418 419 /* if we reach here, valid FRU table is parsed */ 420 break; 421 } 422 423 if (ret < 0) { 424 WARN("FRU table missing for this board\n"); 425 return; 426 } 427 428 for (i = 0; i < BCM_MAX_NR_DDR; i++) { 429 INFO("DDR channel index: %d\n", ddr_info.mcb[i].idx); 430 INFO("DDR size %u GB\n", ddr_info.mcb[i].size_mb / 1024); 431 INFO("DDR ref ID by SW (Not MCB Ref ID) 0x%x\n", 432 ddr_info.mcb[i].ref_id); 433 } 434 435 fru_format_time(board_info.mfg_date, &fru_tm); 436 437 INFO("**** FRU board information ****\n"); 438 INFO("Language 0x%x\n", board_info.lang); 439 INFO("Manufacturing Date %u.%02u.%02u, %02u:%02u\n", 440 fru_tm.year, fru_tm.month, fru_tm.day, 441 fru_tm.hour, fru_tm.min); 442 INFO("Manufacturing Date(Raw) 0x%x\n", board_info.mfg_date); 443 INFO("Manufacturer %s\n", board_info.manufacturer); 444 INFO("Product Name %s\n", board_info.product_name); 445 INFO("Serial number %s\n", board_info.serial_number); 446 INFO("Part number %s\n", board_info.part_number); 447 INFO("File ID %s\n", board_info.file_id); 448 } 449 #endif /* USE_FRU */ 450 451 #ifdef USE_GPIO 452 453 #define INVALID_GPIO 0xffff 454 455 static const int gpio_cfg_bitmap[MAX_NR_GPIOS] = { 456 #ifdef BRD_DETECT_GPIO_BIT0 457 BRD_DETECT_GPIO_BIT0, 458 #else 459 INVALID_GPIO, 460 #endif 461 #ifdef BRD_DETECT_GPIO_BIT1 462 BRD_DETECT_GPIO_BIT1, 463 #else 464 INVALID_GPIO, 465 #endif 466 #ifdef BRD_DETECT_GPIO_BIT2 467 BRD_DETECT_GPIO_BIT2, 468 #else 469 INVALID_GPIO, 470 #endif 471 #ifdef BRD_DETECT_GPIO_BIT3 472 BRD_DETECT_GPIO_BIT3, 473 #else 474 INVALID_GPIO, 475 #endif 476 }; 477 478 static uint8_t gpio_bitmap; 479 480 /* 481 * Use an odd number to avoid potential conflict with public GPIO level 482 * defines 483 */ 484 #define GPIO_STATE_FLOAT 15 485 486 /* 487 * If GPIO_SUPPORT_FLOAT_DETECTION is disabled, simply return GPIO level 488 * 489 * If GPIO_SUPPORT_FLOAT_DETECTION is enabled, add additional test for possible 490 * pin floating (unconnected) scenario. This support is assuming externally 491 * applied pull up / pull down will have a stronger pull than the internal pull 492 * up / pull down. 493 */ 494 static uint8_t gpio_get_state(int gpio) 495 { 496 uint8_t val; 497 498 /* set direction to GPIO input */ 499 gpio_set_direction(gpio, GPIO_DIR_IN); 500 501 #ifndef GPIO_SUPPORT_FLOAT_DETECTION 502 if (gpio_get_value(gpio) == GPIO_LEVEL_HIGH) 503 val = GPIO_LEVEL_HIGH; 504 else 505 val = GPIO_LEVEL_LOW; 506 507 return val; 508 #else 509 /* 510 * Enable internal pull down. If GPIO level is still high, there must 511 * be an external pull up 512 */ 513 gpio_set_pull(gpio, GPIO_PULL_DOWN); 514 if (gpio_get_value(gpio) == GPIO_LEVEL_HIGH) { 515 val = GPIO_LEVEL_HIGH; 516 goto exit; 517 } 518 519 /* 520 * Enable internal pull up. If GPIO level is still low, there must 521 * be an external pull down 522 */ 523 gpio_set_pull(gpio, GPIO_PULL_UP); 524 if (gpio_get_value(gpio) == GPIO_LEVEL_LOW) { 525 val = GPIO_LEVEL_LOW; 526 goto exit; 527 } 528 529 /* if reached here, the pin must be not connected */ 530 val = GPIO_STATE_FLOAT; 531 532 exit: 533 /* make sure internall pull is disabled */ 534 if (gpio_get_pull(gpio) != GPIO_PULL_NONE) 535 gpio_set_pull(gpio, GPIO_PULL_NONE); 536 537 return val; 538 #endif 539 } 540 541 static void board_detect_gpio(void) 542 { 543 unsigned int i, val; 544 int gpio; 545 546 iproc_gpio_init(IPROC_GPIO_S_BASE, IPROC_GPIO_NR, 547 IPROC_IOPAD_MODE_BASE, HSLS_IOPAD_BASE); 548 549 gpio_bitmap = 0; 550 for (i = 0; i < MAX_NR_GPIOS; i++) { 551 if (gpio_cfg_bitmap[i] == INVALID_GPIO) 552 continue; 553 554 /* 555 * Construct the bitmap based on GPIO value. Floating pin 556 * detection is a special case. As soon as a floating pin is 557 * detected, a special value of MAX_GPIO_BITMAP_VAL is 558 * assigned and we break out of the loop immediately 559 */ 560 gpio = gpio_cfg_bitmap[i]; 561 val = gpio_get_state(gpio); 562 if (val == GPIO_STATE_FLOAT) { 563 gpio_bitmap = MAX_GPIO_BITMAP_VAL; 564 break; 565 } 566 567 if (val == GPIO_LEVEL_HIGH) 568 gpio_bitmap |= BIT(i); 569 } 570 571 memcpy(&ddr_info, &gpio_ddr_info[gpio_bitmap], sizeof(ddr_info)); 572 INFO("Board detection GPIO bitmap = 0x%x\n", gpio_bitmap); 573 } 574 #endif /* USE_GPIO */ 575 576 static void bcm_board_detect(void) 577 { 578 #ifdef DDR_LEGACY_MCB_SUPPORTED 579 /* Loading default DDR info */ 580 memcpy(&ddr_info, &default_ddr_info, sizeof(ddr_info)); 581 #endif 582 #ifdef USE_FRU 583 board_detect_fru(); 584 #endif 585 #ifdef USE_GPIO 586 board_detect_gpio(); 587 #endif 588 } 589 590 static void dump_persistent_regs(void) 591 { 592 NOTICE("pr0: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG0)); 593 NOTICE("pr1: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG1)); 594 NOTICE("pr2: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG2)); 595 NOTICE("pr3: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG3)); 596 NOTICE("pr4: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG4)); 597 NOTICE("pr5: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG5)); 598 NOTICE("pr6: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG6)); 599 NOTICE("pr7: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG7)); 600 NOTICE("pr8: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG8)); 601 NOTICE("pr9: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG9)); 602 NOTICE("pr10: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG10)); 603 NOTICE("pr11: %x\n", mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG11)); 604 } 605 606 void plat_bcm_bl2_plat_arch_setup(void) 607 { 608 if (chip_get_rev_id_major() == CHIP_REV_MAJOR_AX) { 609 if (!(sotp_mem_read(SOTP_ATF_CFG_ROW_ID, SOTP_ROW_NO_ECC) & 610 SOTP_ATF_WATCHDOG_ENABLE_MASK)) { 611 /* 612 * Stop sp805 watchdog timer immediately. 613 * It might has been set up by MCU patch earlier for 614 * eMMC workaround. 615 * 616 * Note the watchdog timer started in CRMU has a very 617 * short timeout and needs to be stopped immediately. 618 * Down below we restart it with a much longer timeout 619 * for BL2 and BL31 620 */ 621 sp805_stop(ARM_SP805_TWDG_BASE); 622 } 623 } 624 625 #if !BRCM_DISABLE_TRUSTED_WDOG 626 /* 627 * start secure watchdog for BL2 and BL31. 628 * Note that UART download can take a longer time, 629 * so do not allow watchdog for UART download, 630 * as this boot source is not a standard modus operandi. 631 */ 632 if (boot_source_get() != BOOT_SOURCE_UART) 633 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 634 #endif 635 636 #ifdef BCM_ELOG 637 /* Ensure logging is started out fresh in BL2. */ 638 mmio_write_32(BCM_ELOG_BL2_BASE, 0); 639 #endif 640 /* 641 * In BL2, since we have very limited space to store logs, we only 642 * save logs that are >= the WARNING level. 643 */ 644 bcm_elog_init((void *)BCM_ELOG_BL2_BASE, BCM_ELOG_BL2_SIZE, 645 LOG_LEVEL_WARNING); 646 647 dump_persistent_regs(); 648 649 /* Read CRMU mailbox 0 */ 650 NOTICE("RESET (reported by CRMU): 0x%x\n", 651 mmio_read_32(CRMU_READ_MAIL_BOX0)); 652 653 /* 654 * All non-boot-source PADs are in forced input-mode at 655 * reset so clear the force on non-boot-source PADs using 656 * CDRU register. 657 */ 658 mmio_clrbits_32((uintptr_t)CDRU_CHIP_IO_PAD_CONTROL, 659 (1 << CDRU_CHIP_IO_PAD_CONTROL__CDRU_IOMUX_FORCE_PAD_IN_R)); 660 661 #if DRIVER_OCOTP_ENABLE 662 bcm_otpc_init(&otp_stingray_map); 663 #endif 664 665 set_swreg_based_on_otp(); 666 667 #if IHOST_PLL_FREQ != 0 668 bcm_set_ihost_pll_freq(0x0, IHOST_PLL_FREQ); 669 #endif 670 671 #ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE 672 /* The erasable unit of the eMMC is the "Erase Group"; 673 * Erase group is measured in write blocks which are the 674 * basic writable units of the Device. 675 * The size of the Erase Group is a Device specific parameter 676 */ 677 emmc_erase(EMMC_ERASE_START_BLOCK, EMMC_ERASE_BLOCK_COUNT, 678 EMMC_ERASE_PARTITION); 679 #endif 680 681 bcm_board_detect(); 682 #ifdef DRIVER_EMMC_ENABLE 683 /* Initialize the card, if it is not */ 684 if (bcm_emmc_init(true) < 0) 685 WARN("eMMC Card Initialization Failed!!!\n"); 686 #endif 687 688 #if BL2_TEST_I2C 689 i2c_test(); 690 #endif 691 692 #ifdef USE_DDR 693 ddr_initialize(&ddr_info); 694 695 ddr_secure_region_config(SECURE_DDR_BASE_ADDRESS, 696 SECURE_DDR_END_ADDRESS); 697 #ifdef NITRO_SECURE_ACCESS 698 ddr_secure_region_config(DDR_NITRO_SECURE_REGION_START, 699 DDR_NITRO_SECURE_REGION_END); 700 #endif 701 #else 702 ext_sram_init(); 703 #endif 704 705 #if BL2_TEST_MEM 706 ddr_test(); 707 #endif 708 709 #ifdef USE_NAND 710 brcm_stingray_nand_init(); 711 #endif 712 713 #if defined(USE_PAXB) || defined(USE_PAXC) || defined(USE_SATA) 714 brcm_stingray_pcie_reset(); 715 #endif 716 717 #ifdef USE_PAXC 718 if (boot_source_get() != BOOT_SOURCE_QSPI) 719 brcm_stingray_chimp_check_and_fastboot(); 720 #endif 721 722 #if ((!CLEAN_DDR || MMU_DISABLED)) 723 /* 724 * Now DDR has been initialized. We want to copy all the logs in SRAM 725 * into DDR so we will have much more space to store the logs in the 726 * next boot stage 727 */ 728 bcm_elog_copy_log((void *)BCM_ELOG_BL31_BASE, 729 MIN(BCM_ELOG_BL2_SIZE, BCM_ELOG_BL31_SIZE) 730 ); 731 732 /* 733 * We are not yet at the end of BL2, but we can stop log here so we do 734 * not need to add 'bcm_elog_exit' to the standard BL2 code. The 735 * benefit of capturing BL2 logs after this is very minimal in a 736 * production system 737 * NOTE: BL2 logging must be exited before going forward to setup 738 * page tables 739 */ 740 bcm_elog_exit(); 741 #endif 742 } 743