1# 2# Copyright (c) 2019-2020, Broadcom 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Set the toc_flags to 1 for 100% speed operation 8# Set the toc_flags to 2 for 50% speed operation 9# Set the toc_flags to 3 for 25% speed operation 10# Set the toc_flags bit 3 to indicate ignore the fip in UEFI copy mode 11PLAT_TOC_FLAGS := 0x0 12 13# Set the IHOST_PLL_FREQ to, 14# 1 for full speed 15# 2 for 50% speed 16# 3 for 25% speed 17# 0 for bypass 18$(eval $(call add_define_val,IHOST_PLL_FREQ,1)) 19 20# Enable workaround for ERRATA_A72_859971 21ERRATA_A72_859971 := 1 22 23# Cache Coherency Interconnect Driver needed 24DRIVER_CC_ENABLE := 1 25$(eval $(call add_define,DRIVER_CC_ENABLE)) 26 27# Enable to erase eMMC 28INCLUDE_EMMC_DRIVER_ERASE_CODE := 0 29 30ifeq (${INCLUDE_EMMC_DRIVER_ERASE_CODE},1) 31$(eval $(call add_define,INCLUDE_EMMC_DRIVER_ERASE_CODE)) 32endif 33 34# BL31 is in DRAM 35ARM_BL31_IN_DRAM := 1 36 37ifneq (${USE_EMULATOR},yes) 38STINGRAY_EMULATION_SETUP := 0 39ifeq (${FASTBOOT_TYPE},) 40override FASTBOOT_TYPE := 0 41endif 42USE_PAXB := yes 43USE_PAXC := yes 44USE_CHIMP := yes 45endif 46 47USE_CRMU_SRAM := yes 48 49# Disable FS4 clocks - they can be reenabled when needed by linux 50FS4_DISABLE_CLOCK := yes 51 52# Enable error logging by default for Stingray 53BCM_ELOG := yes 54 55# Enable FRU support by default for Stingray 56ifeq (${USE_FRU},) 57USE_FRU := no 58endif 59 60# Use single cluster 61ifeq (${USE_SINGLE_CLUSTER},yes) 62$(info Using Single Cluster) 63$(eval $(call add_define,USE_SINGLE_CLUSTER)) 64endif 65 66# Use DDR 67ifeq (${USE_DDR},yes) 68$(info Using DDR) 69$(eval $(call add_define,USE_DDR)) 70endif 71 72ifeq (${BOARD_CFG},) 73BOARD_CFG := bcm958742k 74endif 75 76# Use PAXB 77ifeq (${USE_PAXB},yes) 78$(info Using PAXB) 79$(eval $(call add_define,USE_PAXB)) 80endif 81 82# Use FS4 83ifeq (${USE_FS4},yes) 84$(info Using FS4) 85$(eval $(call add_define,USE_FS4)) 86endif 87 88# Use FS6 89ifeq (${USE_FS6},yes) 90$(info Using FS6) 91$(eval $(call add_define,USE_FS6)) 92endif 93 94# Disable FS4 clock 95ifeq (${FS4_DISABLE_CLOCK},yes) 96$(info Using FS4_DISABLE_CLOCK) 97$(eval $(call add_define,FS4_DISABLE_CLOCK)) 98endif 99 100ifneq (${NCSI_IO_DRIVE_STRENGTH_MA},) 101$(info Using NCSI_IO_DRIVE_STRENGTH_MA) 102$(eval $(call add_define,NCSI_IO_DRIVE_STRENGTH_MA)) 103endif 104 105# Use NAND 106ifeq (${USE_NAND},$(filter yes, ${USE_NAND})) 107$(info Using NAND) 108$(eval $(call add_define,USE_NAND)) 109endif 110 111# Enable Broadcom error logging support 112ifeq (${BCM_ELOG},yes) 113$(info Using BCM_ELOG) 114$(eval $(call add_define,BCM_ELOG)) 115endif 116 117# BL31 build for standalone mode 118ifeq (${STANDALONE_BL31},yes) 119RESET_TO_BL31 := 1 120$(info Using RESET_TO_BL31) 121endif 122 123# BL31 force full frequency for all CPUs 124ifeq (${BL31_FORCE_CPU_FULL_FREQ},yes) 125$(info Using BL31_FORCE_CPU_FULL_FREQ) 126$(eval $(call add_define,BL31_FORCE_CPU_FULL_FREQ)) 127endif 128 129# Enable non-secure accesses to CCN registers 130ifeq (${BL31_CCN_NONSECURE},yes) 131$(info Using BL31_CCN_NONSECURE) 132$(eval $(call add_define,BL31_CCN_NONSECURE)) 133endif 134 135# Use ChiMP 136ifeq (${USE_CHIMP},yes) 137$(info Using ChiMP) 138$(eval $(call add_define,USE_CHIMP)) 139endif 140 141# Use PAXC 142ifeq (${USE_PAXC},yes) 143$(info Using PAXC) 144$(eval $(call add_define,USE_PAXC)) 145ifeq (${CHIMPFW_USE_SIDELOAD},yes) 146$(info Using ChiMP FW sideload) 147$(eval $(call add_define,CHIMPFW_USE_SIDELOAD)) 148endif 149$(eval $(call add_define,FASTBOOT_TYPE)) 150$(eval $(call add_define,CHIMP_FB1_ENTRY)) 151endif 152 153ifeq (${DEFAULT_SWREG_CONFIG}, 1) 154$(eval $(call add_define,DEFAULT_SWREG_CONFIG)) 155endif 156 157ifeq (${CHIMP_ALWAYS_NEEDS_QSPI},yes) 158$(eval $(call add_define,CHIMP_ALWAYS_NEEDS_QSPI)) 159endif 160 161# For testing purposes, use memsys stubs. Remove once memsys is fully tested. 162USE_MEMSYS_STUBS := yes 163 164# Default, use BL1_RW area 165ifneq (${BL2_USE_BL1_RW},no) 166$(eval $(call add_define,USE_BL1_RW)) 167endif 168 169# Default soft reset is L3 170$(eval $(call add_define,CONFIG_SOFT_RESET_L3)) 171 172# Enable Chip OTP driver 173DRIVER_OCOTP_ENABLE := 1 174 175include plat/brcm/board/common/board_common.mk 176 177SOC_DIR := brcm/board/stingray 178 179PLAT_INCLUDES += -Iplat/${SOC_DIR}/include/ \ 180 -Iinclude/plat/brcm/common/ \ 181 -Iplat/brcm/common/ 182 183PLAT_BL_COMMON_SOURCES += lib/cpus/aarch64/cortex_a72.S \ 184 plat/${SOC_DIR}/aarch64/plat_helpers.S \ 185 drivers/ti/uart/aarch64/16550_console.S \ 186 plat/${SOC_DIR}/src/tz_sec.c \ 187 drivers/arm/tzc/tzc400.c \ 188 plat/${SOC_DIR}/driver/plat_emmc.c \ 189 plat/${SOC_DIR}/src/topology.c 190 191ifeq (${USE_CHIMP},yes) 192PLAT_BL_COMMON_SOURCES += drivers/brcm/chimp.c 193endif 194 195BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \ 196 plat/${SOC_DIR}/src/bl2_setup.c \ 197 plat/${SOC_DIR}/driver/swreg.c 198 199 200ifeq (${USE_DDR},yes) 201PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include 202else 203PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ext_sram_init 204BL2_SOURCES += plat/${SOC_DIR}/driver/ext_sram_init/ext_sram_init.c 205endif 206 207# Include GICv3 driver files 208include drivers/arm/gic/v3/gicv3.mk 209 210BRCM_GIC_SOURCES := ${GICV3_SOURCES} \ 211 plat/common/plat_gicv3.c \ 212 plat/brcm/common/brcm_gicv3.c 213 214BL31_SOURCES += \ 215 drivers/arm/ccn/ccn.c \ 216 plat/brcm/board/common/timer_sync.c \ 217 plat/brcm/common/brcm_ccn.c \ 218 plat/common/plat_psci_common.c \ 219 plat/${SOC_DIR}/driver/ihost_pll_config.c \ 220 plat/${SOC_DIR}/src/bl31_setup.c \ 221 plat/${SOC_DIR}/src/fsx.c \ 222 plat/${SOC_DIR}/src/iommu.c \ 223 plat/${SOC_DIR}/src/sdio.c \ 224 ${BRCM_GIC_SOURCES} 225 226ifneq (${NCSI_IO_DRIVE_STRENGTH_MA},) 227BL31_SOURCES += plat/${SOC_DIR}/src/ncsi.c 228endif 229 230ifeq (${USE_PAXB},yes) 231BL31_SOURCES += plat/${SOC_DIR}/src/paxb.c 232BL31_SOURCES += plat/${SOC_DIR}/src/sr_paxb_phy.c 233endif 234 235ifeq (${USE_PAXC},yes) 236BL31_SOURCES += plat/${SOC_DIR}/src/paxc.c 237endif 238 239ifdef SCP_BL2 240PLAT_INCLUDES += -Iplat/brcm/common/ 241 242BL2_SOURCES += plat/brcm/common/brcm_mhu.c \ 243 plat/brcm/common/brcm_scpi.c \ 244 plat/${SOC_DIR}/src/scp_utils.c \ 245 plat/${SOC_DIR}/src/scp_cmd.c \ 246 drivers/brcm/scp.c 247 248BL31_SOURCES += plat/brcm/common/brcm_mhu.c \ 249 plat/brcm/common/brcm_scpi.c \ 250 plat/${SOC_DIR}/src/brcm_pm_ops.c 251else 252BL31_SOURCES += plat/${SOC_DIR}/src/ihost_pm.c \ 253 plat/${SOC_DIR}/src/pm.c 254endif 255 256ifeq (${ELOG_SUPPORT},1) 257ifeq (${ELOG_STORE_MEDIA},DDR) 258BL2_SOURCES += plat/brcm/board/common/bcm_elog_ddr.c 259endif 260endif 261 262ifeq (${BL31_BOOT_PRELOADED_SCP}, 1) 263ifdef SCP_BL2 264SCP_CFG_DIR=$(dir ${SCP_BL2}) 265PLAT_INCLUDES += -I${SCP_CFG_DIR} 266endif 267PLAT_INCLUDES += -Iplat/brcm/common/ 268 269# By default use OPTEE Assigned memory 270PRELOADED_SCP_BASE ?= 0x8E000000 271PRELOADED_SCP_SIZE ?= 0x10000 272$(eval $(call add_define,PRELOADED_SCP_BASE)) 273$(eval $(call add_define,PRELOADED_SCP_SIZE)) 274$(eval $(call add_define,BL31_BOOT_PRELOADED_SCP)) 275BL31_SOURCES += plat/${SOC_DIR}/src/scp_utils.c \ 276 plat/${SOC_DIR}/src/scp_cmd.c \ 277 drivers/brcm/scp.c 278endif 279 280# Do not execute the startup code on warm reset. 281PROGRAMMABLE_RESET_ADDRESS := 1 282 283# Nitro FW, config and Crash log uses secure DDR memory 284# Inaddition to above, Nitro master and slave is also secure 285ifneq ($(NITRO_SECURE_ACCESS),) 286$(eval $(call add_define,NITRO_SECURE_ACCESS)) 287$(eval $(call add_define,DDR_NITRO_SECURE_REGION_START)) 288$(eval $(call add_define,DDR_NITRO_SECURE_REGION_END)) 289endif 290