1# 2# Copyright (c) 2019-2020, Broadcom 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Enable workaround for ERRATA_A72_859971 8ERRATA_A72_859971 := 1 9 10# Cache Coherency Interconnect Driver needed 11DRIVER_CC_ENABLE := 1 12$(eval $(call add_define,DRIVER_CC_ENABLE)) 13 14USE_CRMU_SRAM := yes 15 16# Use single cluster 17ifeq (${USE_SINGLE_CLUSTER},yes) 18$(info Using Single Cluster) 19$(eval $(call add_define,USE_SINGLE_CLUSTER)) 20endif 21 22ifeq (${BOARD_CFG},) 23BOARD_CFG := bcm958742k 24endif 25 26# For testing purposes, use memsys stubs. Remove once memsys is fully tested. 27USE_MEMSYS_STUBS := yes 28 29# Default, use BL1_RW area 30ifneq (${BL2_USE_BL1_RW},no) 31$(eval $(call add_define,USE_BL1_RW)) 32endif 33 34# Default soft reset is L3 35$(eval $(call add_define,CONFIG_SOFT_RESET_L3)) 36 37include plat/brcm/board/common/board_common.mk 38 39SOC_DIR := brcm/board/stingray 40 41PLAT_INCLUDES += -Iplat/${SOC_DIR}/include/ \ 42 -Iinclude/plat/brcm/common/ \ 43 -Iplat/brcm/common/ 44 45PLAT_BL_COMMON_SOURCES += lib/cpus/aarch64/cortex_a72.S \ 46 plat/${SOC_DIR}/aarch64/plat_helpers.S \ 47 drivers/ti/uart/aarch64/16550_console.S \ 48 drivers/arm/tzc/tzc400.c 49