xref: /rk3399_ARM-atf/plat/brcm/board/stingray/platform.mk (revision 3942d3a8ea0c1deda44e0bb481876f03b256e25d) 
1#
2# Copyright (c) 2019-2020, Broadcom
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# Set the toc_flags to 1 for 100% speed operation
8# Set the toc_flags to 2 for 50% speed operation
9# Set the toc_flags to 3 for 25% speed operation
10# Set the toc_flags bit 3 to indicate ignore the fip in UEFI copy mode
11PLAT_TOC_FLAGS := 0x0
12
13# Set the IHOST_PLL_FREQ to,
14# 1 for full speed
15# 2 for 50% speed
16# 3 for 25% speed
17# 0 for bypass
18$(eval $(call add_define_val,IHOST_PLL_FREQ,1))
19
20# Enable workaround for ERRATA_A72_859971
21ERRATA_A72_859971 := 1
22
23# Cache Coherency Interconnect Driver needed
24DRIVER_CC_ENABLE := 1
25$(eval $(call add_define,DRIVER_CC_ENABLE))
26
27# BL31 is in DRAM
28ARM_BL31_IN_DRAM	:=	1
29
30ifneq (${USE_EMULATOR},yes)
31STINGRAY_EMULATION_SETUP	:=	0
32ifeq (${FASTBOOT_TYPE},)
33override FASTBOOT_TYPE		:=	0
34endif
35USE_PAXB := yes
36USE_PAXC := yes
37USE_CHIMP := yes
38endif
39
40USE_CRMU_SRAM := yes
41
42# Disable FS4 clocks - they can be reenabled when needed by linux
43FS4_DISABLE_CLOCK := yes
44
45# Enable error logging by default for Stingray
46BCM_ELOG := yes
47
48# Enable FRU support by default for Stingray
49ifeq (${USE_FRU},)
50USE_FRU := no
51endif
52
53# Use single cluster
54ifeq (${USE_SINGLE_CLUSTER},yes)
55$(info Using Single Cluster)
56$(eval $(call add_define,USE_SINGLE_CLUSTER))
57endif
58
59# Use DDR
60ifeq (${USE_DDR},yes)
61$(info Using DDR)
62$(eval $(call add_define,USE_DDR))
63endif
64
65ifeq (${BOARD_CFG},)
66BOARD_CFG := bcm958742k
67endif
68
69# Use PAXB
70ifeq (${USE_PAXB},yes)
71$(info Using PAXB)
72$(eval $(call add_define,USE_PAXB))
73endif
74
75# Use FS4
76ifeq (${USE_FS4},yes)
77$(info Using FS4)
78$(eval $(call add_define,USE_FS4))
79endif
80
81# Use FS6
82ifeq (${USE_FS6},yes)
83$(info Using FS6)
84$(eval $(call add_define,USE_FS6))
85endif
86
87# Disable FS4 clock
88ifeq (${FS4_DISABLE_CLOCK},yes)
89$(info Using FS4_DISABLE_CLOCK)
90$(eval $(call add_define,FS4_DISABLE_CLOCK))
91endif
92
93ifneq (${NCSI_IO_DRIVE_STRENGTH_MA},)
94$(info Using NCSI_IO_DRIVE_STRENGTH_MA)
95$(eval $(call add_define,NCSI_IO_DRIVE_STRENGTH_MA))
96endif
97
98# Use NAND
99ifeq (${USE_NAND},$(filter yes, ${USE_NAND}))
100$(info Using NAND)
101$(eval $(call add_define,USE_NAND))
102endif
103
104# Enable Broadcom error logging support
105ifeq (${BCM_ELOG},yes)
106$(info Using BCM_ELOG)
107$(eval $(call add_define,BCM_ELOG))
108endif
109
110# BL31 build for standalone mode
111ifeq (${STANDALONE_BL31},yes)
112RESET_TO_BL31 := 1
113$(info Using RESET_TO_BL31)
114endif
115
116# BL31 force full frequency for all CPUs
117ifeq (${BL31_FORCE_CPU_FULL_FREQ},yes)
118$(info Using BL31_FORCE_CPU_FULL_FREQ)
119$(eval $(call add_define,BL31_FORCE_CPU_FULL_FREQ))
120endif
121
122# Enable non-secure accesses to CCN registers
123ifeq (${BL31_CCN_NONSECURE},yes)
124$(info Using BL31_CCN_NONSECURE)
125$(eval $(call add_define,BL31_CCN_NONSECURE))
126endif
127
128# Use ChiMP
129ifeq (${USE_CHIMP},yes)
130$(info Using ChiMP)
131$(eval $(call add_define,USE_CHIMP))
132endif
133
134# Use PAXC
135ifeq (${USE_PAXC},yes)
136$(info Using PAXC)
137$(eval $(call add_define,USE_PAXC))
138ifeq (${CHIMPFW_USE_SIDELOAD},yes)
139$(info Using ChiMP FW sideload)
140$(eval $(call add_define,CHIMPFW_USE_SIDELOAD))
141endif
142$(eval $(call add_define,FASTBOOT_TYPE))
143$(eval $(call add_define,CHIMP_FB1_ENTRY))
144endif
145
146ifeq (${DEFAULT_SWREG_CONFIG}, 1)
147$(eval $(call add_define,DEFAULT_SWREG_CONFIG))
148endif
149
150ifeq (${CHIMP_ALWAYS_NEEDS_QSPI},yes)
151$(eval $(call add_define,CHIMP_ALWAYS_NEEDS_QSPI))
152endif
153
154# For testing purposes, use memsys stubs.  Remove once memsys is fully tested.
155USE_MEMSYS_STUBS := yes
156
157# Default, use BL1_RW area
158ifneq (${BL2_USE_BL1_RW},no)
159$(eval $(call add_define,USE_BL1_RW))
160endif
161
162# Default soft reset is L3
163$(eval $(call add_define,CONFIG_SOFT_RESET_L3))
164
165# Enable Chip OTP driver
166DRIVER_OCOTP_ENABLE := 1
167
168include plat/brcm/board/common/board_common.mk
169
170SOC_DIR			:= 	brcm/board/stingray
171
172PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/include/ \
173				-Iinclude/plat/brcm/common/ \
174				-Iplat/brcm/common/
175
176PLAT_BL_COMMON_SOURCES	+=	lib/cpus/aarch64/cortex_a72.S \
177				plat/${SOC_DIR}/aarch64/plat_helpers.S \
178				drivers/ti/uart/aarch64/16550_console.S \
179				plat/${SOC_DIR}/src/tz_sec.c \
180				drivers/arm/tzc/tzc400.c \
181				plat/${SOC_DIR}/src/topology.c
182
183ifeq (${USE_CHIMP},yes)
184PLAT_BL_COMMON_SOURCES	+=	drivers/brcm/chimp.c
185endif
186
187BL2_SOURCES		+=	plat/${SOC_DIR}/driver/ihost_pll_config.c \
188				plat/${SOC_DIR}/src/bl2_setup.c \
189				plat/${SOC_DIR}/driver/swreg.c
190
191
192ifeq (${USE_DDR},yes)
193PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/driver/ddr/soc/include
194else
195PLAT_INCLUDES		+=	-Iplat/${SOC_DIR}/driver/ext_sram_init
196BL2_SOURCES		+=	plat/${SOC_DIR}/driver/ext_sram_init/ext_sram_init.c
197endif
198
199# Include GICv3 driver files
200include drivers/arm/gic/v3/gicv3.mk
201
202BRCM_GIC_SOURCES	:=	${GICV3_SOURCES}		\
203				plat/common/plat_gicv3.c	\
204				plat/brcm/common/brcm_gicv3.c
205
206BL31_SOURCES		+=	\
207				drivers/arm/ccn/ccn.c \
208				plat/brcm/board/common/timer_sync.c \
209				plat/brcm/common/brcm_ccn.c \
210				plat/common/plat_psci_common.c \
211				plat/${SOC_DIR}/driver/ihost_pll_config.c \
212				plat/${SOC_DIR}/src/bl31_setup.c \
213				plat/${SOC_DIR}/src/fsx.c \
214				plat/${SOC_DIR}/src/iommu.c \
215				plat/${SOC_DIR}/src/sdio.c \
216				${BRCM_GIC_SOURCES}
217
218ifneq (${NCSI_IO_DRIVE_STRENGTH_MA},)
219BL31_SOURCES   +=      plat/${SOC_DIR}/src/ncsi.c
220endif
221
222ifeq (${USE_PAXB},yes)
223BL31_SOURCES   +=      plat/${SOC_DIR}/src/paxb.c
224BL31_SOURCES   +=      plat/${SOC_DIR}/src/sr_paxb_phy.c
225endif
226
227ifeq (${USE_PAXC},yes)
228BL31_SOURCES   +=      plat/${SOC_DIR}/src/paxc.c
229endif
230
231ifdef SCP_BL2
232PLAT_INCLUDES		+=	-Iplat/brcm/common/
233
234BL2_SOURCES		+=	plat/brcm/common/brcm_mhu.c \
235				plat/brcm/common/brcm_scpi.c \
236				plat/${SOC_DIR}/src/scp_utils.c \
237				plat/${SOC_DIR}/src/scp_cmd.c \
238				drivers/brcm/scp.c
239
240BL31_SOURCES		+=	plat/brcm/common/brcm_mhu.c \
241				plat/brcm/common/brcm_scpi.c \
242				plat/${SOC_DIR}/src/brcm_pm_ops.c
243else
244BL31_SOURCES		+=	plat/${SOC_DIR}/src/ihost_pm.c \
245				plat/${SOC_DIR}/src/pm.c
246endif
247
248ifeq (${ELOG_SUPPORT},1)
249ifeq (${ELOG_STORE_MEDIA},DDR)
250BL2_SOURCES		+=	plat/brcm/board/common/bcm_elog_ddr.c
251endif
252endif
253
254ifeq (${BL31_BOOT_PRELOADED_SCP}, 1)
255ifdef SCP_BL2
256SCP_CFG_DIR=$(dir ${SCP_BL2})
257PLAT_INCLUDES	+=	-I${SCP_CFG_DIR}
258endif
259PLAT_INCLUDES	+=	-Iplat/brcm/common/
260
261# By default use OPTEE Assigned memory
262PRELOADED_SCP_BASE ?= 0x8E000000
263PRELOADED_SCP_SIZE ?= 0x10000
264$(eval $(call add_define,PRELOADED_SCP_BASE))
265$(eval $(call add_define,PRELOADED_SCP_SIZE))
266$(eval $(call add_define,BL31_BOOT_PRELOADED_SCP))
267BL31_SOURCES += plat/${SOC_DIR}/src/scp_utils.c \
268		plat/${SOC_DIR}/src/scp_cmd.c \
269		drivers/brcm/scp.c
270endif
271
272# Do not execute the startup code on warm reset.
273PROGRAMMABLE_RESET_ADDRESS	:=	1
274
275# Nitro FW, config and Crash log uses secure DDR memory
276# Inaddition to above, Nitro master and slave is also secure
277ifneq ($(NITRO_SECURE_ACCESS),)
278$(eval $(call add_define,NITRO_SECURE_ACCESS))
279$(eval $(call add_define,DDR_NITRO_SECURE_REGION_START))
280$(eval $(call add_define,DDR_NITRO_SECURE_REGION_END))
281endif
282