1*f29d1e0cSSheetal Tigadoli /* 2*f29d1e0cSSheetal Tigadoli * Copyright (c) 2017 - 2020, Broadcom 3*f29d1e0cSSheetal Tigadoli * 4*f29d1e0cSSheetal Tigadoli * SPDX-License-Identifier: BSD-3-Clause 5*f29d1e0cSSheetal Tigadoli */ 6*f29d1e0cSSheetal Tigadoli 7*f29d1e0cSSheetal Tigadoli #ifndef SWREG_H 8*f29d1e0cSSheetal Tigadoli #define SWREG_H 9*f29d1e0cSSheetal Tigadoli 10*f29d1e0cSSheetal Tigadoli /* default voltage if no valid OTP */ 11*f29d1e0cSSheetal Tigadoli #define VDDC_CORE_DEF_VOLT 910000 /* 0.91v */ 12*f29d1e0cSSheetal Tigadoli #define IHOST_DEF_VOLT 940000 /* 0.94v */ 13*f29d1e0cSSheetal Tigadoli 14*f29d1e0cSSheetal Tigadoli #define B0_VDDC_CORE_DEF_VOLT 950000 /* 0.95v */ 15*f29d1e0cSSheetal Tigadoli #define B0_IHOST_DEF_VOLT 950000 /* 0.95v */ 16*f29d1e0cSSheetal Tigadoli #define B0_DDR_VDDC_DEF_VOLT 1000000 /* 1v */ 17*f29d1e0cSSheetal Tigadoli 18*f29d1e0cSSheetal Tigadoli #define SWREG_IHOST1_DIS 4 19*f29d1e0cSSheetal Tigadoli #define SWREG_IHOST1_REG_RESETB 5 20*f29d1e0cSSheetal Tigadoli #define SWREG_IHOST1_PMU_STABLE 2 21*f29d1e0cSSheetal Tigadoli 22*f29d1e0cSSheetal Tigadoli enum sw_reg { 23*f29d1e0cSSheetal Tigadoli DDR_VDDC = 1, 24*f29d1e0cSSheetal Tigadoli IHOST03, 25*f29d1e0cSSheetal Tigadoli IHOST12, 26*f29d1e0cSSheetal Tigadoli IHOST_ARRAY, 27*f29d1e0cSSheetal Tigadoli DDRIO_SLAVE, 28*f29d1e0cSSheetal Tigadoli VDDC_CORE, 29*f29d1e0cSSheetal Tigadoli VDDC1, 30*f29d1e0cSSheetal Tigadoli DDRIO_MASTER 31*f29d1e0cSSheetal Tigadoli }; 32*f29d1e0cSSheetal Tigadoli 33*f29d1e0cSSheetal Tigadoli int set_swreg(enum sw_reg reg_id, uint32_t micro_volts); 34*f29d1e0cSSheetal Tigadoli int swreg_firmware_update(void); 35*f29d1e0cSSheetal Tigadoli 36*f29d1e0cSSheetal Tigadoli #endif 37