1 /* 2 * Copyright (c) 2015-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <brcm_def.h> 15 16 #include <cmn_plat_def.h> 17 18 #include "sr_def.h" 19 20 /* 21 * Most platform porting definitions provided by included headers 22 */ 23 #define PLAT_BRCM_SCP_TZC_DRAM1_SIZE ULL(0x0) 24 25 /* 26 * Required by standard platform porting definitions 27 */ 28 #define PLATFORM_CLUSTER0_CORE_COUNT 2 29 #define PLATFORM_CLUSTER1_CORE_COUNT 2 30 #define PLATFORM_CLUSTER2_CORE_COUNT 2 31 #define PLATFORM_CLUSTER3_CORE_COUNT 2 32 33 #define BRCM_SYSTEM_COUNT 1 34 #define BRCM_CLUSTER_COUNT 4 35 36 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 37 PLATFORM_CLUSTER1_CORE_COUNT+ \ 38 PLATFORM_CLUSTER2_CORE_COUNT+ \ 39 PLATFORM_CLUSTER3_CORE_COUNT) 40 41 #define PLAT_NUM_PWR_DOMAINS (BRCM_SYSTEM_COUNT + \ 42 BRCM_CLUSTER_COUNT + \ 43 PLATFORM_CORE_COUNT) 44 45 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 46 47 /* TBD-STINGRAY */ 48 #define CACHE_WRITEBACK_SHIFT 6 49 /* 50 * Some data must be aligned on the biggest cache line size in the platform. 51 * This is known only to the platform as it might have a combination of 52 * integrated and external caches. 53 */ 54 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 55 56 /* TBD-STINGRAY */ 57 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 58 59 #define BL1_PLATFORM_STACK_SIZE 0x3300 60 #define BL2_PLATFORM_STACK_SIZE 0xc000 61 #define BL11_PLATFORM_STACK_SIZE 0x2b00 62 #define DEFAULT_PLATFORM_STACK_SIZE 0x400 63 #if IMAGE_BL1 64 # define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE 65 #else 66 #if IMAGE_BL2 67 #ifdef USE_BL1_RW 68 # define PLATFORM_STACK_SIZE BL2_PLATFORM_STACK_SIZE 69 #else 70 # define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE 71 #endif 72 #else 73 #if IMAGE_BL11 74 # define PLATFORM_STACK_SIZE BL11_PLATFORM_STACK_SIZE 75 #else 76 # define PLATFORM_STACK_SIZE DEFAULT_PLATFORM_STACK_SIZE 77 #endif 78 #endif 79 #endif 80 81 #define PLAT_BRCM_TRUSTED_SRAM_BASE 0x66D00000 82 #define PLAT_BRCM_TRUSTED_SRAM_SIZE 0x00040000 83 84 #ifdef RUN_BL1_FROM_QSPI /* BL1 XIP from QSPI */ 85 # define PLAT_BRCM_TRUSTED_ROM_BASE QSPI_BASE_ADDR 86 #elif RUN_BL1_FROM_NAND /* BL1 XIP from NAND */ 87 # define PLAT_BRCM_TRUSTED_ROM_BASE NAND_BASE_ADDR 88 #else /* BL1 executed in ROM */ 89 # define PLAT_BRCM_TRUSTED_ROM_BASE ROM_BASE_ADDR 90 #endif 91 #define PLAT_BRCM_TRUSTED_ROM_SIZE 0x00040000 92 93 /******************************************************************************* 94 * BL1 specific defines. 95 ******************************************************************************/ 96 #define BL1_RO_BASE PLAT_BRCM_TRUSTED_ROM_BASE 97 #define BL1_RO_LIMIT (PLAT_BRCM_TRUSTED_ROM_BASE \ 98 + PLAT_BRCM_TRUSTED_ROM_SIZE) 99 100 /* 101 * Put BL1 RW at the beginning of the Trusted SRAM. 102 */ 103 #define BL1_RW_BASE (BRCM_BL_RAM_BASE) 104 #define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000) 105 106 #define BL11_RW_BASE BL1_RW_LIMIT 107 #define BL11_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 108 PLAT_BRCM_TRUSTED_SRAM_SIZE) 109 110 /******************************************************************************* 111 * BL2 specific defines. 112 ******************************************************************************/ 113 #if RUN_BL2_FROM_QSPI /* BL2 XIP from QSPI */ 114 #define BL2_BASE QSPI_BASE_ADDR 115 #define BL2_LIMIT (BL2_BASE + 0x40000) 116 #define BL2_RW_BASE BL1_RW_LIMIT 117 #define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 118 PLAT_BRCM_TRUSTED_SRAM_SIZE) 119 #elif RUN_BL2_FROM_NAND /* BL2 XIP from NAND */ 120 #define BL2_BASE NAND_BASE_ADDR 121 #define BL2_LIMIT (BL2_BASE + 0x40000) 122 #define BL2_RW_BASE BL1_RW_LIMIT 123 #define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 124 PLAT_BRCM_TRUSTED_SRAM_SIZE) 125 #else 126 #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) 127 #define BL2_LIMIT (BRCM_BL_RAM_BASE + BRCM_BL_RAM_SIZE) 128 #endif 129 130 /* 131 * BL1 persistent area in internal SRAM 132 * This area will increase as more features gets into BL1 133 */ 134 #define BL1_PERSISTENT_DATA_SIZE 0x2000 135 136 /* To reduce BL2 runtime footprint, we can re-use some BL1_RW area */ 137 #define BL1_RW_RECLAIM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 138 BL1_PERSISTENT_DATA_SIZE) 139 140 /******************************************************************************* 141 * BL3-1 specific defines. 142 ******************************************************************************/ 143 /* Max Size of BL31 (in DRAM) */ 144 #define PLAT_BRCM_MAX_BL31_SIZE 0x30000 145 146 #ifdef USE_DDR 147 #define BL31_BASE BRCM_AP_TZC_DRAM1_BASE 148 149 #define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \ 150 PLAT_BRCM_MAX_BL31_SIZE) 151 #else 152 /* Put BL3-1 at the end of external on-board SRAM connected as NOR flash */ 153 #define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \ 154 PLAT_BRCM_MAX_BL31_SIZE) 155 156 #define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE) 157 #endif 158 159 #define SECURE_DDR_END_ADDRESS BL31_LIMIT 160 161 #ifdef NEED_SCP_BL2 162 #define SCP_BL2_BASE BL31_BASE 163 #define PLAT_MAX_SCP_BL2_SIZE 0x9000 164 #define PLAT_SCP_COM_SHARED_MEM_BASE (CRMU_SHARED_SRAM_BASE) 165 /* dummy defined */ 166 #define PLAT_BRCM_MHU_BASE 0x0 167 #endif 168 169 #define SECONDARY_CPU_SPIN_BASE_ADDR BRCM_SHARED_RAM_BASE 170 171 /* Generic system timer counter frequency */ 172 #ifndef SYSCNT_FREQ 173 #define SYSCNT_FREQ (125 * 1000 * 1000) 174 #endif 175 176 /* 177 * Enable the BL32 definitions, only when optee os is selected as secure 178 * payload (BL32). 179 */ 180 #ifdef SPD_opteed 181 /* 182 * Reserved Memory Map : SHMEM & TZDRAM. 183 * 184 * +--------+----------+ 0x8D000000 185 * | SHMEM (NS) | 16MB 186 * +-------------------+ 0x8E000000 187 * | | TEE_RAM(S)| 4MB 188 * + TZDRAM +----------+ 0x8E400000 189 * | | TA_RAM(S) | 12MB 190 * +-------------------+ 0x8F000000 191 * | BL31 Binary (S) | 192KB 192 * +-------------------+ 0x8F030000 193 */ 194 195 #define BL32_VA_SIZE (4 * 1024 * 1024) 196 #define BL32_BASE (0x8E000000) 197 #define BL32_LIMIT (BL32_BASE + BL32_VA_SIZE) 198 #define TSP_SEC_MEM_BASE BL32_BASE 199 #define TSP_SEC_MEM_SIZE BL32_VA_SIZE 200 #endif 201 202 #ifdef SPD_opteed 203 #define SECURE_DDR_BASE_ADDRESS BL32_BASE 204 #else 205 #define SECURE_DDR_BASE_ADDRESS BL31_BASE 206 #endif 207 /******************************************************************************* 208 * Platform specific page table and MMU setup constants 209 ******************************************************************************/ 210 211 #define MAX_XLAT_TABLES 7 212 213 #define PLAT_BRCM_MMAP_ENTRIES 10 214 215 #define MAX_MMAP_REGIONS (PLAT_BRCM_MMAP_ENTRIES + \ 216 BRCM_BL_REGIONS) 217 218 #ifdef USE_DDR 219 #ifdef BL33_OVERRIDE_LOAD_ADDR 220 #define PLAT_BRCM_NS_IMAGE_OFFSET BL33_OVERRIDE_LOAD_ADDR 221 #else 222 /* 223 * BL3-3 image starting offset. 224 * Putting start of DRAM as of now. 225 */ 226 #define PLAT_BRCM_NS_IMAGE_OFFSET 0x80000000 227 #endif /* BL33_OVERRIDE_LOAD_ADDR */ 228 #else 229 /* 230 * BL3-3 image starting offset. 231 * Putting start of external on-board SRAM as of now. 232 */ 233 #define PLAT_BRCM_NS_IMAGE_OFFSET NOR_BASE_ADDR 234 #endif /* USE_DDR */ 235 /****************************************************************************** 236 * Required platform porting definitions common to all BRCM platforms 237 *****************************************************************************/ 238 239 #define MAX_IO_DEVICES 5 240 #define MAX_IO_HANDLES 6 241 242 #define PRIMARY_CPU 0 243 244 /* GIC Parameter */ 245 #define PLAT_BRCM_GICD_BASE GIC500_BASE 246 #define PLAT_BRCM_GICR_BASE (GIC500_BASE + 0x200000) 247 248 /* Define secure interrupt as per Group here */ 249 #define PLAT_BRCM_G1S_IRQ_PROPS(grp) \ 250 INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 251 GIC_INTR_CFG_EDGE), \ 252 INTR_PROP_DESC(BRCM_IRQ_SEC_SPI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 253 GIC_INTR_CFG_EDGE) 254 255 #define PLAT_BRCM_G0_IRQ_PROPS(grp) \ 256 INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 257 GIC_INTR_CFG_EDGE), \ 258 259 /* 260 *CCN 502 related constants. 261 */ 262 #define PLAT_BRCM_CLUSTER_COUNT 4 /* Number of RN-F Masters */ 263 #define PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP CLUSTER0_NODE_ID, CLUSTER1_NODE_ID, CLUSTER2_NODE_ID, CLUSTER3_NODE_ID 264 #define CCN_SIZE 0x1000000 265 #define CLUSTER0_NODE_ID 1 266 #define CLUSTER1_NODE_ID 7 267 #define CLUSTER2_NODE_ID 9 268 #define CLUSTER3_NODE_ID 15 269 270 #endif 271