1 /* 2 * Copyright (c) 2015-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <brcm_def.h> 15 16 #include <cmn_plat_def.h> 17 18 #include "sr_def.h" 19 20 /* 21 * Most platform porting definitions provided by included headers 22 */ 23 #define PLAT_BRCM_SCP_TZC_DRAM1_SIZE ULL(0x0) 24 25 /* 26 * Required by standard platform porting definitions 27 */ 28 #define PLATFORM_CLUSTER0_CORE_COUNT 2 29 #define PLATFORM_CLUSTER1_CORE_COUNT 2 30 #define PLATFORM_CLUSTER2_CORE_COUNT 2 31 #define PLATFORM_CLUSTER3_CORE_COUNT 2 32 #define PLATFORM_CLUSTER4_CORE_COUNT 2 33 34 #define BRCM_SYSTEM_COUNT 1 35 #define BRCM_CLUSTER_COUNT 5 36 37 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 38 PLATFORM_CLUSTER1_CORE_COUNT+ \ 39 PLATFORM_CLUSTER2_CORE_COUNT+ \ 40 PLATFORM_CLUSTER3_CORE_COUNT+ \ 41 PLATFORM_CLUSTER4_CORE_COUNT) 42 43 #define PLAT_NUM_PWR_DOMAINS (BRCM_SYSTEM_COUNT + \ 44 BRCM_CLUSTER_COUNT + \ 45 PLATFORM_CORE_COUNT) 46 47 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 48 49 /* TBD-STINGRAY */ 50 #define CACHE_WRITEBACK_SHIFT 6 51 /* 52 * Some data must be aligned on the biggest cache line size in the platform. 53 * This is known only to the platform as it might have a combination of 54 * integrated and external caches. 55 */ 56 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 57 58 /* TBD-STINGRAY */ 59 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 60 61 #define BL1_PLATFORM_STACK_SIZE 0x3300 62 #define BL2_PLATFORM_STACK_SIZE 0xc000 63 #define BL11_PLATFORM_STACK_SIZE 0x2b00 64 #define DEFAULT_PLATFORM_STACK_SIZE 0x400 65 #if IMAGE_BL1 66 # define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE 67 #else 68 #if IMAGE_BL2 69 #ifdef USE_BL1_RW 70 # define PLATFORM_STACK_SIZE BL2_PLATFORM_STACK_SIZE 71 #else 72 # define PLATFORM_STACK_SIZE BL1_PLATFORM_STACK_SIZE 73 #endif 74 #else 75 #if IMAGE_BL11 76 # define PLATFORM_STACK_SIZE BL11_PLATFORM_STACK_SIZE 77 #else 78 # define PLATFORM_STACK_SIZE DEFAULT_PLATFORM_STACK_SIZE 79 #endif 80 #endif 81 #endif 82 83 #define PLAT_BRCM_TRUSTED_SRAM_BASE 0x66D00000 84 #define PLAT_BRCM_TRUSTED_SRAM_SIZE 0x00040000 85 86 #ifdef RUN_BL1_FROM_QSPI /* BL1 XIP from QSPI */ 87 # define PLAT_BRCM_TRUSTED_ROM_BASE QSPI_BASE_ADDR 88 #elif RUN_BL1_FROM_NAND /* BL1 XIP from NAND */ 89 # define PLAT_BRCM_TRUSTED_ROM_BASE NAND_BASE_ADDR 90 #else /* BL1 executed in ROM */ 91 # define PLAT_BRCM_TRUSTED_ROM_BASE ROM_BASE_ADDR 92 #endif 93 #define PLAT_BRCM_TRUSTED_ROM_SIZE 0x00040000 94 95 /******************************************************************************* 96 * BL1 specific defines. 97 ******************************************************************************/ 98 #define BL1_RO_BASE PLAT_BRCM_TRUSTED_ROM_BASE 99 #define BL1_RO_LIMIT (PLAT_BRCM_TRUSTED_ROM_BASE \ 100 + PLAT_BRCM_TRUSTED_ROM_SIZE) 101 102 /* 103 * Put BL1 RW at the beginning of the Trusted SRAM. 104 */ 105 #define BL1_RW_BASE (BRCM_BL_RAM_BASE) 106 #define BL1_RW_LIMIT (BL1_RW_BASE + 0x12000) 107 108 #define BL11_RW_BASE BL1_RW_LIMIT 109 #define BL11_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 110 PLAT_BRCM_TRUSTED_SRAM_SIZE) 111 112 /******************************************************************************* 113 * BL2 specific defines. 114 ******************************************************************************/ 115 #if RUN_BL2_FROM_QSPI /* BL2 XIP from QSPI */ 116 #define BL2_BASE QSPI_BASE_ADDR 117 #define BL2_LIMIT (BL2_BASE + 0x40000) 118 #define BL2_RW_BASE BL1_RW_LIMIT 119 #define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 120 PLAT_BRCM_TRUSTED_SRAM_SIZE) 121 #elif RUN_BL2_FROM_NAND /* BL2 XIP from NAND */ 122 #define BL2_BASE NAND_BASE_ADDR 123 #define BL2_LIMIT (BL2_BASE + 0x40000) 124 #define BL2_RW_BASE BL1_RW_LIMIT 125 #define BL2_RW_LIMIT (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 126 PLAT_BRCM_TRUSTED_SRAM_SIZE) 127 #else 128 #define BL2_BASE (BL1_RW_LIMIT + PAGE_SIZE) 129 #define BL2_LIMIT (BRCM_BL_RAM_BASE + BRCM_BL_RAM_SIZE) 130 #endif 131 132 /* 133 * BL1 persistent area in internal SRAM 134 * This area will increase as more features gets into BL1 135 */ 136 #define BL1_PERSISTENT_DATA_SIZE 0x2000 137 138 /* To reduce BL2 runtime footprint, we can re-use some BL1_RW area */ 139 #define BL1_RW_RECLAIM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 140 BL1_PERSISTENT_DATA_SIZE) 141 142 /******************************************************************************* 143 * BL3-1 specific defines. 144 ******************************************************************************/ 145 /* Max Size of BL31 (in DRAM) */ 146 #define PLAT_BRCM_MAX_BL31_SIZE 0x30000 147 148 #ifdef USE_DDR 149 #define BL31_BASE BRCM_AP_TZC_DRAM1_BASE 150 151 #define BL31_LIMIT (BRCM_AP_TZC_DRAM1_BASE + \ 152 PLAT_BRCM_MAX_BL31_SIZE) 153 #else 154 /* Put BL3-1 at the end of external on-board SRAM connected as NOR flash */ 155 #define BL31_BASE (NOR_BASE_ADDR + NOR_SIZE - \ 156 PLAT_BRCM_MAX_BL31_SIZE) 157 158 #define BL31_LIMIT (NOR_BASE_ADDR + NOR_SIZE) 159 #endif 160 161 #define SECURE_DDR_END_ADDRESS BL31_LIMIT 162 163 #ifdef NEED_SCP_BL2 164 #define SCP_BL2_BASE BL31_BASE 165 #define PLAT_MAX_SCP_BL2_SIZE 0x9000 166 #define PLAT_SCP_COM_SHARED_MEM_BASE (CRMU_SHARED_SRAM_BASE) 167 /* dummy defined */ 168 #define PLAT_BRCM_MHU_BASE 0x0 169 #endif 170 171 #define SECONDARY_CPU_SPIN_BASE_ADDR BRCM_SHARED_RAM_BASE 172 173 /* Generic system timer counter frequency */ 174 #ifndef SYSCNT_FREQ 175 #define SYSCNT_FREQ (125 * 1000 * 1000) 176 #endif 177 178 /* 179 * Enable the BL32 definitions, only when optee os is selected as secure 180 * payload (BL32). 181 */ 182 #ifdef SPD_opteed 183 /* 184 * Reserved Memory Map : SHMEM & TZDRAM. 185 * 186 * +--------+----------+ 0x8D000000 187 * | SHMEM (NS) | 16MB 188 * +-------------------+ 0x8E000000 189 * | | TEE_RAM(S)| 4MB 190 * + TZDRAM +----------+ 0x8E400000 191 * | | TA_RAM(S) | 12MB 192 * +-------------------+ 0x8F000000 193 * | BL31 Binary (S) | 192KB 194 * +-------------------+ 0x8F030000 195 */ 196 197 #define BL32_VA_SIZE (4 * 1024 * 1024) 198 #define BL32_BASE (0x8E000000) 199 #define BL32_LIMIT (BL32_BASE + BL32_VA_SIZE) 200 #define TSP_SEC_MEM_BASE BL32_BASE 201 #define TSP_SEC_MEM_SIZE BL32_VA_SIZE 202 #endif 203 204 #ifdef SPD_opteed 205 #define SECURE_DDR_BASE_ADDRESS BL32_BASE 206 #else 207 #define SECURE_DDR_BASE_ADDRESS BL31_BASE 208 #endif 209 /******************************************************************************* 210 * Platform specific page table and MMU setup constants 211 ******************************************************************************/ 212 213 #define MAX_XLAT_TABLES 7 214 215 #define PLAT_BRCM_MMAP_ENTRIES 10 216 217 #define MAX_MMAP_REGIONS (PLAT_BRCM_MMAP_ENTRIES + \ 218 BRCM_BL_REGIONS) 219 220 #ifdef USE_DDR 221 #ifdef BL33_OVERRIDE_LOAD_ADDR 222 #define PLAT_BRCM_NS_IMAGE_OFFSET BL33_OVERRIDE_LOAD_ADDR 223 #else 224 /* 225 * BL3-3 image starting offset. 226 * Putting start of DRAM as of now. 227 */ 228 #define PLAT_BRCM_NS_IMAGE_OFFSET 0x80000000 229 #endif /* BL33_OVERRIDE_LOAD_ADDR */ 230 #else 231 /* 232 * BL3-3 image starting offset. 233 * Putting start of external on-board SRAM as of now. 234 */ 235 #define PLAT_BRCM_NS_IMAGE_OFFSET NOR_BASE_ADDR 236 #endif /* USE_DDR */ 237 /****************************************************************************** 238 * Required platform porting definitions common to all BRCM platforms 239 *****************************************************************************/ 240 241 #define MAX_IO_DEVICES 5 242 #define MAX_IO_HANDLES 6 243 244 #define PRIMARY_CPU 0 245 246 /* GIC Parameter */ 247 #define PLAT_BRCM_GICD_BASE GIC500_BASE 248 #define PLAT_BRCM_GICR_BASE (GIC500_BASE + 0x200000) 249 250 /* Define secure interrupt as per Group here */ 251 #define PLAT_BRCM_G1S_IRQ_PROPS(grp) \ 252 INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 253 GIC_INTR_CFG_EDGE), \ 254 INTR_PROP_DESC(BRCM_IRQ_SEC_SPI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 255 GIC_INTR_CFG_EDGE) 256 257 #define PLAT_BRCM_G0_IRQ_PROPS(grp) \ 258 INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 259 GIC_INTR_CFG_EDGE), \ 260 261 /* 262 *CCN 502 related constants. 263 */ 264 #define PLAT_BRCM_CLUSTER_COUNT 4 /* Number of RN-F Masters */ 265 #define PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP CLUSTER0_NODE_ID, CLUSTER1_NODE_ID, CLUSTER2_NODE_ID, CLUSTER3_NODE_ID 266 #define CCN_SIZE 0x1000000 267 #define CLUSTER0_NODE_ID 1 268 #define CLUSTER1_NODE_ID 7 269 #define CLUSTER2_NODE_ID 9 270 #define CLUSTER3_NODE_ID 15 271 272 #endif 273