1*3942d3a8SSheetal Tigadoli /* 2*3942d3a8SSheetal Tigadoli * Copyright (c) 2016 - 2020, Broadcom 3*3942d3a8SSheetal Tigadoli * 4*3942d3a8SSheetal Tigadoli * SPDX-License-Identifier: BSD-3-Clause 5*3942d3a8SSheetal Tigadoli */ 6*3942d3a8SSheetal Tigadoli 7*3942d3a8SSheetal Tigadoli #ifndef PAXB_H 8*3942d3a8SSheetal Tigadoli #define PAXB_H 9*3942d3a8SSheetal Tigadoli 10*3942d3a8SSheetal Tigadoli /* total number of PCIe cores */ 11*3942d3a8SSheetal Tigadoli #define NUM_OF_SR_PCIE_CORES 8 12*3942d3a8SSheetal Tigadoli #define NUM_OF_NS3Z_PCIE_CORES 1 13*3942d3a8SSheetal Tigadoli 14*3942d3a8SSheetal Tigadoli /* 15*3942d3a8SSheetal Tigadoli * List of PCIe core and PAXB wrapper memory power registers 16*3942d3a8SSheetal Tigadoli */ 17*3942d3a8SSheetal Tigadoli #define PCIE_CORE_BASE 0x40000800 18*3942d3a8SSheetal Tigadoli #define PCIE_CORE_SOFT_RST_CFG_BASE (PCIE_CORE_BASE + 0x40) 19*3942d3a8SSheetal Tigadoli #define PCIE_CORE_SOFT_RST 0x1 20*3942d3a8SSheetal Tigadoli #define PCIE_CORE_ISO_CFG_BASE (PCIE_CORE_BASE + 0x54) 21*3942d3a8SSheetal Tigadoli #define PCIE_CORE_MEM_ISO 0x2 22*3942d3a8SSheetal Tigadoli #define PCIE_CORE_ISO 0x1 23*3942d3a8SSheetal Tigadoli 24*3942d3a8SSheetal Tigadoli #define PCIE_CORE_MEM_PWR_BASE (PCIE_CORE_BASE + 0x58) 25*3942d3a8SSheetal Tigadoli #define PCIE_PAXB_MEM_PWR_BASE (PCIE_CORE_BASE + 0x5c) 26*3942d3a8SSheetal Tigadoli #define PCIE_CORE_PMI_CFG_BASE (PCIE_CORE_BASE + 0x64) 27*3942d3a8SSheetal Tigadoli #define PCIE_CORE_RESERVED_CFG (PCIE_CORE_BASE + 0x6c) 28*3942d3a8SSheetal Tigadoli #define PCIE_CORE_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x74) 29*3942d3a8SSheetal Tigadoli #define PCIE_PAXB_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x78) 30*3942d3a8SSheetal Tigadoli #define PCIE_CORE_PWR_OFFSET 0x100 31*3942d3a8SSheetal Tigadoli 32*3942d3a8SSheetal Tigadoli #define SR_A0_DEVICE_ID 0xd713 33*3942d3a8SSheetal Tigadoli #define SR_B0_DEVICE_ID 0xd714 34*3942d3a8SSheetal Tigadoli /* TODO: Modify device ID once available */ 35*3942d3a8SSheetal Tigadoli #define NS3Z_DEVICE_ID 0xd715 36*3942d3a8SSheetal Tigadoli 37*3942d3a8SSheetal Tigadoli /* FIXME: change link speed to GEN3 when it's ready */ 38*3942d3a8SSheetal Tigadoli #define GEN1_LINK_SPEED 1 39*3942d3a8SSheetal Tigadoli #define GEN2_LINK_SPEED 2 40*3942d3a8SSheetal Tigadoli #define GEN3_LINK_SPEED 3 41*3942d3a8SSheetal Tigadoli 42*3942d3a8SSheetal Tigadoli typedef struct { 43*3942d3a8SSheetal Tigadoli uint32_t type; 44*3942d3a8SSheetal Tigadoli uint32_t device_id; 45*3942d3a8SSheetal Tigadoli uint32_t pipemux_idx; 46*3942d3a8SSheetal Tigadoli uint32_t num_cores; 47*3942d3a8SSheetal Tigadoli int (*pipemux_init)(void); 48*3942d3a8SSheetal Tigadoli int (*phy_init)(void); 49*3942d3a8SSheetal Tigadoli int (*core_needs_enable)(unsigned int core_idx); 50*3942d3a8SSheetal Tigadoli unsigned int (*get_link_width)(unsigned int core_idx); 51*3942d3a8SSheetal Tigadoli unsigned int (*get_link_speed)(void); 52*3942d3a8SSheetal Tigadoli } paxb_cfg; 53*3942d3a8SSheetal Tigadoli 54*3942d3a8SSheetal Tigadoli enum paxb_type { 55*3942d3a8SSheetal Tigadoli PAXB_SR, 56*3942d3a8SSheetal Tigadoli PAXB_NS3Z, 57*3942d3a8SSheetal Tigadoli }; 58*3942d3a8SSheetal Tigadoli 59*3942d3a8SSheetal Tigadoli extern const paxb_cfg *paxb; 60*3942d3a8SSheetal Tigadoli 61*3942d3a8SSheetal Tigadoli #ifdef USE_PAXB 62*3942d3a8SSheetal Tigadoli void paxb_init(void); 63*3942d3a8SSheetal Tigadoli void paxb_rc_cfg_write(unsigned int core_idx, unsigned int where, 64*3942d3a8SSheetal Tigadoli uint32_t val); 65*3942d3a8SSheetal Tigadoli unsigned int paxb_rc_cfg_read(unsigned int core_idx, unsigned int where); 66*3942d3a8SSheetal Tigadoli int pcie_core_needs_enable(unsigned int core_idx); 67*3942d3a8SSheetal Tigadoli const paxb_cfg *paxb_get_sr_config(void); 68*3942d3a8SSheetal Tigadoli #else paxb_init(void)69*3942d3a8SSheetal Tigadolistatic inline void paxb_init(void) 70*3942d3a8SSheetal Tigadoli { 71*3942d3a8SSheetal Tigadoli } 72*3942d3a8SSheetal Tigadoli #endif 73*3942d3a8SSheetal Tigadoli 74*3942d3a8SSheetal Tigadoli #endif /* PAXB_H */ 75