1*717448d6SSheetal Tigadoli /* 2*717448d6SSheetal Tigadoli * Copyright (c) 2015 - 2020, Broadcom 3*717448d6SSheetal Tigadoli * 4*717448d6SSheetal Tigadoli * SPDX-License-Identifier: BSD-3-Clause 5*717448d6SSheetal Tigadoli */ 6*717448d6SSheetal Tigadoli 7*717448d6SSheetal Tigadoli #ifndef CMN_PLAT_DEF_H 8*717448d6SSheetal Tigadoli #define CMN_PLAT_DEF_H 9*717448d6SSheetal Tigadoli 10*717448d6SSheetal Tigadoli /* Print file and line number on assert */ 11*717448d6SSheetal Tigadoli #define PLAT_LOG_LEVEL_ASSERT LOG_LEVEL_INFO 12*717448d6SSheetal Tigadoli 13*717448d6SSheetal Tigadoli /* 14*717448d6SSheetal Tigadoli * The number of regions like RO(code), coherent and data required by 15*717448d6SSheetal Tigadoli * different BL stages which need to be mapped in the MMU. 16*717448d6SSheetal Tigadoli */ 17*717448d6SSheetal Tigadoli #if USE_COHERENT_MEM 18*717448d6SSheetal Tigadoli #define CMN_BL_REGIONS 3 19*717448d6SSheetal Tigadoli #else 20*717448d6SSheetal Tigadoli #define CMN_BL_REGIONS 2 21*717448d6SSheetal Tigadoli #endif 22*717448d6SSheetal Tigadoli 23*717448d6SSheetal Tigadoli /* 24*717448d6SSheetal Tigadoli * FIP definitions 25*717448d6SSheetal Tigadoli */ 26*717448d6SSheetal Tigadoli #define PLAT_FIP_ATTEMPT_OFFSET 0x20000 27*717448d6SSheetal Tigadoli #define PLAT_FIP_NUM_ATTEMPTS 128 28*717448d6SSheetal Tigadoli 29*717448d6SSheetal Tigadoli #define PLAT_BRCM_FIP_QSPI_BASE QSPI_BASE_ADDR 30*717448d6SSheetal Tigadoli #define PLAT_BRCM_FIP_NAND_BASE NAND_BASE_ADDR 31*717448d6SSheetal Tigadoli #define PLAT_BRCM_FIP_MAX_SIZE 0x01000000 32*717448d6SSheetal Tigadoli 33*717448d6SSheetal Tigadoli #define PLAT_BRCM_FIP_BASE PLAT_BRCM_FIP_QSPI_BASE 34*717448d6SSheetal Tigadoli #endif 35