1717448d6SSheetal Tigadoli /* 2717448d6SSheetal Tigadoli * Copyright (c) 2016 - 2020, Broadcom 3717448d6SSheetal Tigadoli * 4717448d6SSheetal Tigadoli * SPDX-License-Identifier: BSD-3-Clause 5717448d6SSheetal Tigadoli */ 6717448d6SSheetal Tigadoli 7717448d6SSheetal Tigadoli #include <brcm_def.h> 8717448d6SSheetal Tigadoli #include <plat_brcm.h> 9717448d6SSheetal Tigadoli 10717448d6SSheetal Tigadoli #if IMAGE_BL2 11717448d6SSheetal Tigadoli const mmap_region_t plat_brcm_mmap[] = { 12717448d6SSheetal Tigadoli HSLS_REGION, 13717448d6SSheetal Tigadoli BRCM_MAP_SHARED_RAM, 14717448d6SSheetal Tigadoli BRCM_MAP_NAND_RO, 15717448d6SSheetal Tigadoli BRCM_MAP_QSPI_RO, 16717448d6SSheetal Tigadoli #ifdef PERIPH0_REGION 17717448d6SSheetal Tigadoli PERIPH0_REGION, 18717448d6SSheetal Tigadoli #endif 19717448d6SSheetal Tigadoli #ifdef PERIPH1_REGION 20717448d6SSheetal Tigadoli PERIPH1_REGION, 21717448d6SSheetal Tigadoli #endif 22717448d6SSheetal Tigadoli #ifdef USE_DDR 23717448d6SSheetal Tigadoli BRCM_MAP_NS_DRAM1, 24717448d6SSheetal Tigadoli #if BRCM_BL31_IN_DRAM 25717448d6SSheetal Tigadoli BRCM_MAP_BL31_SEC_DRAM, 26717448d6SSheetal Tigadoli #endif 27717448d6SSheetal Tigadoli #else 28717448d6SSheetal Tigadoli #ifdef BRCM_MAP_EXT_SRAM 29717448d6SSheetal Tigadoli BRCM_MAP_EXT_SRAM, 30717448d6SSheetal Tigadoli #endif 31717448d6SSheetal Tigadoli #endif 32717448d6SSheetal Tigadoli #if defined(USE_CRMU_SRAM) && defined(CRMU_SRAM_BASE) 33717448d6SSheetal Tigadoli CRMU_SRAM_REGION, 34717448d6SSheetal Tigadoli #endif 35717448d6SSheetal Tigadoli {0} 36717448d6SSheetal Tigadoli }; 37717448d6SSheetal Tigadoli #endif 38717448d6SSheetal Tigadoli 39*9a40c0fbSSheetal Tigadoli #if IMAGE_BL31 40*9a40c0fbSSheetal Tigadoli const mmap_region_t plat_brcm_mmap[] = { 41*9a40c0fbSSheetal Tigadoli HSLS_REGION, 42*9a40c0fbSSheetal Tigadoli #ifdef PERIPH0_REGION 43*9a40c0fbSSheetal Tigadoli PERIPH0_REGION, 44*9a40c0fbSSheetal Tigadoli #endif 45*9a40c0fbSSheetal Tigadoli #ifdef PERIPH1_REGION 46*9a40c0fbSSheetal Tigadoli PERIPH1_REGION, 47*9a40c0fbSSheetal Tigadoli #endif 48*9a40c0fbSSheetal Tigadoli #ifdef PERIPH2_REGION 49*9a40c0fbSSheetal Tigadoli PERIPH2_REGION, 50*9a40c0fbSSheetal Tigadoli #endif 51*9a40c0fbSSheetal Tigadoli #ifdef USB_REGION 52*9a40c0fbSSheetal Tigadoli USB_REGION, 53*9a40c0fbSSheetal Tigadoli #endif 54*9a40c0fbSSheetal Tigadoli #ifdef USE_DDR 55*9a40c0fbSSheetal Tigadoli BRCM_MAP_NS_DRAM1, 56*9a40c0fbSSheetal Tigadoli #ifdef BRCM_MAP_NS_SHARED_DRAM 57*9a40c0fbSSheetal Tigadoli BRCM_MAP_NS_SHARED_DRAM, 58*9a40c0fbSSheetal Tigadoli #endif 59*9a40c0fbSSheetal Tigadoli #else 60*9a40c0fbSSheetal Tigadoli #ifdef BRCM_MAP_EXT_SRAM 61*9a40c0fbSSheetal Tigadoli BRCM_MAP_EXT_SRAM, 62*9a40c0fbSSheetal Tigadoli #endif 63*9a40c0fbSSheetal Tigadoli #endif 64*9a40c0fbSSheetal Tigadoli #if defined(USE_CRMU_SRAM) && defined(CRMU_SRAM_BASE) 65*9a40c0fbSSheetal Tigadoli CRMU_SRAM_REGION, 66*9a40c0fbSSheetal Tigadoli #endif 67*9a40c0fbSSheetal Tigadoli {0} 68*9a40c0fbSSheetal Tigadoli }; 69*9a40c0fbSSheetal Tigadoli #endif 70*9a40c0fbSSheetal Tigadoli 71717448d6SSheetal Tigadoli CASSERT((ARRAY_SIZE(plat_brcm_mmap) - 1) <= PLAT_BRCM_MMAP_ENTRIES, 72717448d6SSheetal Tigadoli assert_plat_brcm_mmap_mismatch); 73717448d6SSheetal Tigadoli CASSERT((PLAT_BRCM_MMAP_ENTRIES + BRCM_BL_REGIONS) <= MAX_MMAP_REGIONS, 74717448d6SSheetal Tigadoli assert_max_mmap_regions); 75