1/* 2 * Copyright (c) 2023, Aspeed Technology Inc. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <arch.h> 10#include <cortex_a35.h> 11#include <platform_def.h> 12 13 .globl plat_is_my_cpu_primary 14 .globl plat_my_core_pos 15 .globl plat_secondary_cold_boot_setup 16 .globl plat_get_syscnt_freq2 17 .globl plat_crash_console_init 18 .globl plat_crash_console_putc 19 .globl plat_crash_console_flush 20 21/* unsigned int plat_is_my_cpu_primary(void); */ 22func plat_is_my_cpu_primary 23 mrs x0, mpidr_el1 24 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 25 cmp x0, #PLATFORM_CORE_PRIMARY 26 cset w0, eq 27 ret 28endfunc plat_is_my_cpu_primary 29 30/* unsigned int plat_my_core_pos(void); */ 31func plat_my_core_pos 32 mrs x0, mpidr_el1 33 mov x2, #PLATFORM_CORE_COUNT_PER_CLUSTER 34 and x1, x0, #MPIDR_CPU_MASK 35 and x0, x0, #MPIDR_CLUSTER_MASK 36 madd x0, x0, x2, x1 37 ret 38endfunc plat_my_core_pos 39 40/* unsigned int plat_get_syscnt_freq2(void); */ 41func plat_get_syscnt_freq2 42 mov_imm w0, PLAT_SYSCNT_CLKIN_HZ 43 ret 44endfunc plat_get_syscnt_freq2 45 46/* int plat_crash_console_init(void); */ 47func plat_crash_console_init 48 mov_imm x0, CONSOLE_UART_BASE 49 mov_imm x1, CONSOLE_UART_CLKIN_HZ 50 mov_imm x2, CONSOLE_UART_BAUDRATE 51 b console_16550_core_init 52endfunc plat_crash_console_init 53 54/* int plat_crash_console_putc(int); */ 55func plat_crash_console_putc 56 mov_imm x1, CONSOLE_UART_BASE 57 b console_16550_core_putc 58endfunc plat_crash_console_putc 59 60/* void plat_crash_console_flush(void); */ 61func plat_crash_console_flush 62 mov_imm x0, CONSOLE_UART_BASE 63 b console_16550_core_flush 64endfunc plat_crash_console_flush 65