1 /* 2 * Copyright (c) 2023, Aspeed Technology Inc. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <common/debug.h> 9 #include <common/desc_image_load.h> 10 #include <drivers/arm/gicv3.h> 11 #include <drivers/console.h> 12 #include <drivers/ti/uart/uart_16550.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <plat/common/platform.h> 15 #include <platform_def.h> 16 17 static console_t console; 18 19 static entry_point_info_t bl32_ep_info; 20 static entry_point_info_t bl33_ep_info; 21 22 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 23 24 static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr) 25 { 26 /* to workaround the return type mismatch */ 27 return plat_core_pos_by_mpidr(mpidr); 28 } 29 30 static const gicv3_driver_data_t plat_gic_data = { 31 .gicd_base = GICD_BASE, 32 .gicr_base = GICR_BASE, 33 .rdistif_num = PLATFORM_CORE_COUNT, 34 .rdistif_base_addrs = rdistif_base_addrs, 35 .mpidr_to_core_pos = plat_mpidr_to_core_pos, 36 }; 37 38 static const mmap_region_t plat_mmap[] = { 39 MAP_REGION_FLAT(GICD_BASE, GICD_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(GICR_BASE, GICR_SIZE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 MAP_REGION_FLAT(UART_BASE, PAGE_SIZE, 44 MT_DEVICE | MT_RW | MT_SECURE), 45 MAP_REGION_FLAT(SCU_CPU_BASE, PAGE_SIZE, 46 MT_DEVICE | MT_RW | MT_SECURE), 47 { 0 } 48 }; 49 50 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 51 u_register_t arg2, u_register_t arg3) 52 { 53 console_16550_register(CONSOLE_UART_BASE, CONSOLE_UART_CLKIN_HZ, 54 CONSOLE_UART_BAUDRATE, &console); 55 56 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); 57 58 bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); 59 } 60 61 void bl31_plat_arch_setup(void) 62 { 63 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 64 BL_CODE_END - BL_CODE_BASE, 65 MT_CODE | MT_SECURE); 66 67 mmap_add_region(BL_CODE_END, BL_CODE_END, 68 BL_END - BL_CODE_END, 69 MT_RW_DATA | MT_SECURE); 70 71 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, 72 MT_MEMORY | MT_RW); 73 74 mmap_add(plat_mmap); 75 76 init_xlat_tables(); 77 78 enable_mmu_el3(0); 79 } 80 81 void bl31_platform_setup(void) 82 { 83 gicv3_driver_init(&plat_gic_data); 84 gicv3_distif_init(); 85 gicv3_rdistif_init(plat_my_core_pos()); 86 gicv3_cpuif_enable(plat_my_core_pos()); 87 } 88 89 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 90 { 91 entry_point_info_t *ep_info; 92 93 ep_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 94 95 if (!ep_info->pc) { 96 return NULL; 97 } 98 99 return ep_info; 100 } 101