1*85f199b7SChia-Wei Wang /* 2*85f199b7SChia-Wei Wang * Copyright (c) 2023, Aspeed Technology Inc. 3*85f199b7SChia-Wei Wang * 4*85f199b7SChia-Wei Wang * SPDX-License-Identifier: BSD-3-Clause 5*85f199b7SChia-Wei Wang */ 6*85f199b7SChia-Wei Wang 7*85f199b7SChia-Wei Wang #ifndef PLATFORM_REG_H 8*85f199b7SChia-Wei Wang #define PLATFORM_REG_H 9*85f199b7SChia-Wei Wang 10*85f199b7SChia-Wei Wang /* GIC */ 11*85f199b7SChia-Wei Wang #define GICD_BASE U(0x12200000) 12*85f199b7SChia-Wei Wang #define GICD_SIZE U(0x10000) 13*85f199b7SChia-Wei Wang #define GICR_BASE U(0x12280000) 14*85f199b7SChia-Wei Wang #define GICR_SIZE U(0x100000) 15*85f199b7SChia-Wei Wang 16*85f199b7SChia-Wei Wang /* UART */ 17*85f199b7SChia-Wei Wang #define UART_BASE U(0x14c33000) 18*85f199b7SChia-Wei Wang #define UART12_BASE (UART_BASE + 0xb00) 19*85f199b7SChia-Wei Wang 20*85f199b7SChia-Wei Wang /* CPU-die SCU */ 21*85f199b7SChia-Wei Wang #define SCU_CPU_BASE U(0x12c02000) 22*85f199b7SChia-Wei Wang #define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) 23*85f199b7SChia-Wei Wang #define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) 24*85f199b7SChia-Wei Wang #define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) 25*85f199b7SChia-Wei Wang #define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) 26*85f199b7SChia-Wei Wang #define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0) 27*85f199b7SChia-Wei Wang 28*85f199b7SChia-Wei Wang #endif /* PLATFORM_REG_H */ 29